Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 688

PAL_PERF_MON_INFO
PAL_PERF_MON_INFO – Get Processor Performance Monitor
Information (15)
Returns Performance Monitor information about what can be counted and how to
Purpose:
configure the monitors to count the desired events.
Static Registers Only
Calling Conv:
Physical and Virtual
Mode:
Not dependent
Buffer:
Arguments:
Argument
index
pm_buffer
Reserved
Reserved
Returns:
Return Value
status
pm_info
Reserved
Reserved
Status:
Status Value
0
-2
-3
PAL_PERF_MON_INFO is called to determine the number of performance monitors and
Description:
the events which can be counted on the performance monitors. For more information
on performance monitoring, see
pm_info is a formatted 64-bit return register, as shown in
Figure 11-40. Layout of pm_info Return Value
.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
retired
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Table 11-110. pm_info Fields
Field
generic
width
cycles
retired
The pm_buffer argument points to a 128-byte memory area where mask information is
returned. The layout of pm_buffer is shown in
Table 11-111. pm_buffer Layout
Offset
0x0
0x20
2:440
Description
Index of PAL_PERF_MON_INFO within the list of PAL procedures.
An address to an 8-byte aligned 128-byte memory buffer.
0
0
Description
Return status of the PAL_PERF_MON_INFO procedure.
Information about the performance monitors implemented.
0
0
Description
Call completed without error
Invalid argument
Call completed with error
Section 7.2, "Performance Monitoring" on page
cycles
Unsigned 8-bit number defining the number of generic PMC/PMD pairs.
Unsigned 8-bit number in the range 0:60 defining the number of implemented counter bits.
Unsigned 8-bit number defining the event type for counting processor cycles.
Unsigned 8-bit number defining the event type for retired instruction bundles.
256-bit mask defining which PMC registers are implemented.
256-bit mask defining which PMD registers are implemented.
Figure
width
reserved
Description
Table 11-111.
Description
Volume 2, Part 1: Processor Abstraction Layer
2:155.
11-40.
8 7 6 5 4 3 2 1 0
generic