Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 715

Hide thumbs Also See for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3:
Table of Contents

Advertisement

PAL_VM_PAGE_SIZE – Get Virtual Memory Page Size Information
(34)
Returns page size information about the virtual memory characteristics of the processor
Purpose:
implementation.
Static Registers Only
Calling Conv:
Physical and Virtual
Mode:
Not dependent
Buffer:
Arguments:
Argument
index
Reserved
Reserved
Reserved
Returns:
Return Value
status
insertable_pages
purge_pages
Reserved
Status:
Status Value
0
-2
-3
The values returned from this call are all 64-bit bitmaps. One bit is set for each page
Description:
size implemented by the processor where bit n represents a page size of 2**n. Please
refer to
Table 4-5 on page 2:58
The insertable_pages returns the page sizes that are supported for TLB insertions and
region registers.
The purge_pages returns the page sizes that are supported for the TLB purge
operations.
Volume 2, Part 1: Processor Abstraction Layer
Description
Index of PAL_VM_PAGE_SIZE within the list of PAL procedures.
0
0
0
Description
Return status of the PAL_VM_PAGE_SIZE procedure.
64-bit vector containing a bit for each architected page size that is supported for TLB
insertions and region registers.
64-bit vector containing a bit for each architected page size supported for TLB purge
operations.
0
Description
Call completed without error.
Invalid argument
Call completed with error.
for the minimum page sizes that are supported.
PAL_VM_PAGE_SIZE
2:467

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

This manual is also suitable for:

Itanium architecture 2.3

Table of Contents