Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 770

A store buffer may not provide a local read operation early access to a value written by
a semaphore operation. Therefore, the outcome r1 = 1, r3 = 1, r2 = 0, r4 = 0, r5 = 0,
and r6 = 0 in the
used in the previous execution.
2.2.1.11 Ordered Cacheable Operations are Seen in the Same Order by All
Observers
The Itanium memory ordering model requires that release stores and semaphore
operations (both acquire and release forms) become visible to all observers in the
coherence domain in a single total order with the exception that each processor may
observe (via loads or acquire loads) its own update early. Thus, each observer in the
coherence domain sees the same interleaving of release stores and semaphores (both
acquire and release forms) from the other processors in the coherence domain except
that each processor may observe its own release stores (via loads or acquire loads)
prior to their being observed globally.
Table 2-14.
Processor #0
st.rel [x] = 1// M1 ld.acq r1 = [x]//M2
The Itanium memory ordering model only disallows the outcome r1 = 1, r3 = 1, r2 = 0,
and r4 = 0 in this execution. By the definition of the Itanium memory ordering
semantics,
The Itanium memory ordering model does not permit the r1 = 1, r3 = 1, r2 = 0, and r4
= 0 outcome as this would require that Processors #1 and #3 observe the release
stores to x and y in different orders. Specifically, assuming that the outcome is r1 = 1,
r3 = 1, r2 = 0, and r4 = 0:
The final two statements are inconsistent since both
true unless Processors #1 and #3 are allowed to see the release stores to x and y in
different orders.
The Itanium memory ordering model allows the r1 = 1, r3 = 1, r2 = 0, and r4 = 0
outcome if either one or both of the release stores M1 and M4 are unordered since
unordered operations need not be seen in the same total order by all observers in the
coherence domain. Thus, in a version of the execution shown in
unordered stores, Processor #2 observes

M4 M1
2:522
Table 2-13 execution is not allowed. The reasoning is similar to that
Enforcing the Same Visibility Order to All Observers in a
Coherence Domain
Processor #1
ld r2 = [y]//M3
Outcome: only r1 = 1, r3 = 1, r2 = 0, and r4 =0 is not allowed
  
r2 = 0 M3 M4 M1
  
r4 = 0 M6 M1 M4
.
Table 2-14 illustrates this behavior.
Processor #2
st.rel [y] = 1// M4 ld.acq r3 = [y]//M5

M2 M3

M5 M6
 
r1 = 1 M1 M2
 
r3 = 1 M4 M5
 
M4 because M1 M2, M2
 
M1 because M4 M5, M5

M1
 while Processor #4 observes
M1 M4
Volume 2, Part 2: MP Coherence and Synchronization
Processor #3
ld r4 = [x]//M6
 
M3, and M3 M4
 
M6, and M6 M1
and  cannot be
M4 M4 M1
Table 2-14 with