Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 612

Table 11-61. Application Register Conventions
Register
BSPSTORE
RNAT
FCR
EFLAG
CSD
SSD
CFLG
FSR
FIR
FDR
CCV
UNAT
FPSR
ITC
RUC
PFS
LC
EC
a. BSP, BSPSTORE, and RNAT may not be changed by PAL, but the value at exit may be different due to RSE
activity. PAL_TEST_PROC is an exception to this rule, and the RSE contents may not be relied on after
making this procedure call.
b. No PAL procedure writes to the ITC. The value at exit is the value at entry plus the elapsed time of the
procedure call.
c. No PAL procedure writes to the RUC. The value at exit is the value at entry plus the number of cycles
provided to the processor during the procedure call.
PAL procedures that use the static calling conventions do not use stacked registers or
the RSE. Therefore RSE internal state and the CFM are unchanged by these procedures.
11.10.2.3 Return Buffers
Any addresses passed to PAL procedures as buffers for return parameters must be
8-byte aligned. Unaligned addresses may cause undefined results.
11.10.2.4 Invalid Arguments
The PAL procedure calling conventions specify rules that must be followed. These rules
specify certain PSR values, they specify that reserved fields and arguments must be
zero filled and specify that values not defined in a range and defined as reserved must
not be used.
If the caller of a PAL procedure does not follow these rules, an invalid argument return
value may be returned or undefined results may occur during the execution of the
procedure. If the caller passes in a PAL procedure index value that is not defined, PAL
will return an Unimplemented procedure (-1) status to the caller.
2:364
Description
Backing Store Pointer for Memory Stores
RSE NaT Collection Register
IA-32 Floating-point Control Registers
IA-32 EFLAG register
IA-32 Code Segment Descriptor
IA-32 Stack Segment Descriptor
IA-32 Combined CR0 and CR4 Register
IA-32 Floating-point Status Register
IA-32 Floating-point Instruction Register
IA-32 Floating-point Data Register
Compare and Exchange Compare Value Register
User NaT Collection Register
Floating-point Status Register
Interval Time Counter
Resource Utilization Counter
Previous Function State
Loop Counter Register
Epilog Counter Register
Class
a
unchanged
a
unchanged
preserved
preserved
preserved
preserved
preserved
preserved
preserved
preserved
scratch
according to GR class
preserved
b
unchanged
c
unchanged
preserved
preserved
preserved
Volume 2, Part 1: Processor Abstraction Layer