Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 323

4.3.3 Instruction Behavior with Unimplemented Addresses
The use of an unimplemented address affects instruction execution as described in the
bullet list below. If instruction address translation is enabled, an "unimplemented
address" refers to an unimplemented virtual address. If instruction address translation
is disabled, an "unimplemented address" refers to an unimplemented physical address.
• Non-speculative memory references (non-speculative loads, stores, and
semaphores), the following non-access references: fc, fc.i, tpa, lfetch.fault,
and probe.fault, and mandatory RSE operations to unimplemented addresses
result in an Unimplemented Data Address fault.
• Virtual addresses used by instruction and data TLB purge/insert operations are
checked, and if the base address (register r3 of the purge, IFA for inserts) targets
an unimplemented virtual address, a Unimplemented Data Address fault is raised.
The page size of the insert or purge is ignored.
• Speculative loads from unimplemented addresses always return a NaT bit in the
target register.
• A regular_form probe instruction to an unimplemented address returns zero in the
target register.
• A tak instruction to an unimplemented address returns one in the target register.
• A non-faulting lfetch to an unimplemented address is silently ignored.
• Eager RSE operations to unimplemented addresses do not fault.
• Execution of a taken branch, taken chk, or an rfi to an unimplemented address, or
execution of a non-branching slot 2 instruction in a bundle at the upper edge of the
implemented address space (where the next sequential bundle address would be an
unimplemented address) results either in an Unimplemented Instruction Address
trap on the branch, chk, rfi or non-branching slot 2 instruction, or in an
Unimplemented Instruction Address fault on the fetch of the unimplemented
address.
• When ptc.g or ptc.ga operations place a virtual address on the bus, the virtual
address is sign-extended to a full 64-bit format. If an incoming ptc.g or ptc.ga
presents a virtual address base that targets an unimplemented virtual address, the
upper (unimplemented) virtual address bits are dropped, and the purge is
performed with the truncated address.
• The behavior of executing vmsw.1 in a bundle whose address will become
unimplemented after PSR.vm is set to 1 is undefined.
4.4 Memory Attributes
When virtual addressing is enabled, memory attributes defining the speculative,
cacheability and write-policies of the virtually mapped physical page are defined by the
TLB. When physical addressing is enabled, memory attributes are supplied as described
in "Physical Addressing Memory Attributes" on page
4.4.1 Virtual Addressing Memory Attributes
For virtual memory references, the memory attribute field of each virtual translation
describes physical memory properties as shown in
Volume 2, Part 1: Addressing and Protection
2:76.
Table 4-11.
2:75