Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 543

• test_status
failures when the state field returns a value of PERFORMANCE RESTRICTED or
FUNCTIONALLY RESTRICTED. The value returned is implementation dependent.
11.2.3 PAL Self-test Control Word
The PAL self-test control word is a 48-bit value. This bit field is defined in
Figure 11-10. Self-test Control Word
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
• test_control
the user control over the length and runtime of the processor self-tests. This control
word is ordered from the longest running tests up to the shortest running tests with
bit 0 controlling the longest running test.
PAL may not implement all 47-bits of the test_control word. PAL communicates if a
bit provides control by placing a zero in that bit. If a bit provides no control, PAL will
place a one in it.
PAL will have two sets of test_control bits for the two phases of the processor
self-test.
PAL provides information about implemented test_control bits at the hand-off from
PAL to SAL for the firmware recovery check. These test_control bits provide control
for phase one of processor self-test. It also provides this information via the PAL
procedure call PAL_TEST_INFO for both the phase one and phase two processor
tests depending on which information the caller is requesting.
PAL interprets these bits as input parameters on two occasions. The first time is
when SAL passes control back to PAL after the firmware recovery check. The
second time is when a call to PAL_TEST_PROC is made. When PAL interprets these
bits it will only interpret implemented test_control bits and will ignore the values
located in the unimplemented test_control bits.
PAL interprets the implemented bits such that if a bit contains a zero, this indicates
to run the test. If a bit contains a one, this indicates to PAL to skip the test.
If the cs bit indicates that control is not available, the test_control bits will be
ignored or generate an illegal argument in procedure calls if the caller sets these
bits.
• cs Control Support: This bit defines if an implementation supports control of the
–
PAL self-tests via the self-test control word. If this bit is 0, the implementation does
not support control of the processor self-tests via the self-test control word. If this
bit is 1, the implementation does support control of the processor self-tests via the
self-test control word.
If control is not supported, GR37 will be ignored at the hand-off between SAL and
PAL after the firmware recovery check and the PAL procedures related to the
processor self-tests may return illegal arguments if a user tries to use the self-test
control features.
Volume 2, Part 1: Processor Abstraction Layer
An unsigned 32-bit-field providing additional information on test
–
reserved
This is an ordered implementation-specific control word that allows
–
16 15 14 13 12 11 10 9
test_control
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
cs
Figure 11-10.
8 7 6 5 4 3 2 1
test_control
2:295
0