Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 840

8.1.2.3 Denormal/Unnormal Operand Exception (Fault)
The exception-enabled response of the Itanium arithmetic instruction to a
Denormal/Unnormal Operand exception is to leave the operands unchanged and to set
the D bit in the ISR.code field of the ISR register. The operating system kernel, reached
via the floating-point fault vector, will then invoke the user floating-point exception
handler, if one has been registered.
8.1.2.4 Overflow Exception (Trap)
The exception-enabled response of an Itanium floating-point arithmetic instruction to
an Overflow exception is to deliver the first (exponent unbounded) IEEE rounded result,
and to set the O bit (and possibly the I and FPA bits) in the ISR.code field of the ISR
register and the Overflow flags (and possibly the Inexact flag) in the appropriate status
field of the FPSR register.
The IEEE-754 standard requires that, when raising an overflow exception, the user
handler should be provided with the result rounded to the destination precision with the
exponent range unbounded. For the huge result to fit in the destination's range, it must
be scaled down by a factor equal to 2.0
of bits in the exponent of the floating-point format used to represent the result.) This
scaling down will bring the result close to the middle of the range covered by the
particular format. The exponent adjustment factors to do the scaling for the various
formats are determined as follows:
• 8-bit (single) exponents are adjusted by 3*2
• 11-bit (double) exponents are adjusted by 3*2
• 15-bit (double-extended) exponents are adjusted by 3*2
• 17-bit (register) exponents are adjusted by 3*2
The actual scaling of the result is not performed by the Itanium architecture. The IEEE
filter that is invoked before calling the user floating-point exception handler typically
performs the scaling.
8.1.2.5 Underflow Exception (Trap)
The exception-enabled response of an Itanium floating-point arithmetic instruction to
an Underflow exception is to deliver the first (exponent unbounded) IEEE rounded
result, and to set the U bit (and possibly the I and FPA bits) in the ISR.code field of the
ISR register and the Underflow flag (and possibly the Inexact flag) in the appropriate
status field of the FPSR register.
The IEEE-754 standard requires that, when raising an underflow exception, the user
handler should be provided with the result rounded to the destination precision with the
exponent range unbounded. For the tiny result to fit in the destination's range, it must
be scaled up by a factor equal to 2.0
bits in the exponent of the floating-point format used to represent the result). The
scaling up will bring result close to the middle of the range covered by the particular
format. The exponent adjustment factors to do this scaling for the various formats are
the same as those for enabled overflow exceptions, listed above.
2:592
a
(with a equal to 3*2
6
= 0xc0 = 192.
9
= 0x600 = 1536.
15
= 0x18000 = 98304.
a n-2
(with a equal to 3*2
Volume 2, Part 2: Floating-point System Software
n-2
, where n is the number
13
= 0x6000 = 24576.
, where n is the number of