Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 505

Table 10-5.
IA-32 Instruction
HLT
IDIV
IMUL
IN, INS
INC
INT 3, INTO
INT n
INVD
INVLPG
IRET, IRETD
Jcc
JMP
JMPE
LAHF
LAR
LDMXCSR
LDS, LES, LFS, LGS,
LSS
LEA
LEAVE
LGDT, LLDT
LIDT
LMSW
Lock prefix
LODS
LOOP, LOOPcc
LSL
LTR
MASKMOVQ
MAXPS, MAXSS, MINPS,
MINSS
MOV
MOVNTPS, MOVNTQ
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Volume 2, Part 1: Itanium Architecture-based Operating System Interaction Model with IA-32 Applications
IA-32 Instruction Summary (Continued)
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Intel Itanium System
Environment
Instruction Intercept
unchanged
unchanged + I/O ports are
mapped virtually
unchanged
Mandatory Exception vector
#
Mandatory Interruption vector
#
Instruction Intercept
Real Mode: Instruction
Intercept
to VM86: Instruction Intercept
from VM86: Instruction
Intercept
same privilege: Instruction
Intercept
less privilege: Instruction
Intercept
different task: Instruction
Intercept
additional taken branch trap
near: no change
far: no change
gate task: Gate Intercept
call gate: Gate Intercept
additional taken branch trap
unchanged
Instruction Intercept
Optional Lock Intercept
unchanged
additional taken branch trap
unchanged
Instruction Intercept
unchanged
Comments
IA-32 privileged instruction
If CFLG.io is 0, the TSS I/O permission bitmap is
not consulted. Intel Itanium TLB faults control
accessibility to I/O ports.
Delivered as an IA_32_Interrupt
Delivered as an IA_32_Exception
IA-32 privilege instruction
All forms of IRET result in an instruction intercept
If PSR.tb is 1, raise a taken branch trap.
Intercept fault if through a call or task gate
If PSR.tb is 1, raise a taken branch trap.
Jumps to the Intel Itanium instruction set
IA-32 privileged register resource
If Locks are disabled (DCR.lc is 1) and a processor
external lock transaction is required
If PSR.tb is 1, raise a taken branch trap.
User level instruction
IA-32 privileged register
2:257