Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 810

region register; they are not inserted into the TLB. Likewise, when software purges a
translation from the processor's TLBs, the VRN bits of the address used for the purge
are used only to index the corresponding region register and are not used to find a
matching translation. Only the RID and VPN bits are used to find overlapping
translations in the TLBs.
The fact that the VRN bits are not contained in the processor TLB allows the same
address space (identified by a RID) to be referenced through any of the eight region
registers. In other words, the combination of RID and VPN establishes a unique 85-bit
virtual address, regardless of which VRN (and region register) was used to form the
pair. Independence of VRN allows easy creation of temporary virtual mappings of an
address space and can accelerate cross-address space copying as described in
Section 5.1.1.3.
5.1.1.1 RID Management
Before a RID that has been used for one address space can be reused for another
address space, all TLB entries relating to the first address space have to be purged. In
general, this will require a complete flush of the TLBs of all processors in the system.
This can be accomplished by performing an IPI to all processors and executing the ptc.e
loop described in
A more efficient alternative, depending on the size of the defunct address space, might
be to perform a series of ptc.ga operations on one processor to tear down just the
translations used by the recycled RID. Some processor implementations support an
efficient region-wide purge page size such that this can be accomplished with a single
ptc.ga operation.
The frequency of these global TLB flushes can be reduced by using a RID allocation
strategy that maximizes the time between use and reuse of a RID. For example, RIDs
could be assigned by using a counter that is as wide as the number of implemented RID
bits and that is incremented after every assignment. Only when the RID counter wraps
around it is necessary to do a global TLB flush. After the flush the operating system can
either remember the in-use RIDs or it can re-assign new RIDs to all currently active
address spaces.
5.1.1.2 Multiple Address Space Operating Systems
Multiple address space (MAS) operating systems provide a separate address space for
each process. Typically, only when a process is running is its address space visible to
software.
The application view of the virtual address space in the MAS OS model is a contiguous
64-bit address space, though normally not all of this virtual address space is accessible
by the application. At least one of the 8 regions must be used to map the OS itself so
that the OS can handle interruptions and system services invoked by the application.
The OS chooses a region ID and a region (e.g. region 7) into which to map itself during
the boot process and usually does not change this mapping after enabling address
translation. The other seven regions may be used to map process-private code and
data; code and data that are shared amongst multiple processes; to map large files;
temporary mappings to allow efficient cross-address space copies (see
Section 5.1.1.3); and, for operating systems which use it, the long format VHPT.
2:562
Section 5.2.2.2.2 on each processor in the TLB coherence domain.
Volume 2, Part 2: Memory Management