Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 537

11.2 PAL Power On/Reset
11.2.1 PALE_RESET
The purpose of PALE_RESET is to initialize and test the processor. Upon receipt of a
power-on/reset event the processor begins executing code from the PALE_RESET
entrypoint in the firmware address space. PALE_RESET initializes the processor and
may perform a minimal processor self test. PAL may optionally perform authentication
of the PAL firmware to ensure data integrity. If the authentication code runs cacheable
by default, then a processor-specific mechanism will be provided to disable caching for
diagnostic purposes.
PALE_RESET then branches to SALE_ENTRY to determine if a recovery condition exists,
which would require an update of the firmware. If it does, SALE_ENTRY performs the
update and resets the system. If no firmware recovery is needed, SAL returns to
PALE_RESET to perform the processor self-tests and initialization. SAL can control the
length and coverage of the PAL processor self-test by examining and modifying the
self-test control word passed to SAL at the firmware recovery hand-off state. Please see
Section 11.2.3, "PAL Self-test Control Word" for more information on the self-test
control word.
The PAL processor self-tests are split into two phases. The first phase is written to test
processor features that do not require external memory to be present to execute
correctly. These tests are automatically run when SAL returns to PAL after the branch to
SALE_ENTRY for a firmware recovery check. This section is referred to as phase one of
processor self-test and they are generally run early during the processor boot process.
The second phase is written requiring that external memory is available to execute
correctly. These tests are run when a call to the PAL procedure PAL_TEST_PROC is
made with the correct parameters set up. These tests are referred to as phase two of
processor self-test since they are usually run later in the processor boot process after
external memory has been initialized on the platform.
PAL may execute IA-32 instructions to fully test and initialize the processor. This IA-32
code will not generate any special IA-32 bus transactions nor will it require any special
platform features to correctly execute. PAL then branches to SALE_ENTRY to conduct
platform initialization and testing before loading the operating system software.
11.2.2 PALE_RESET Exit State
• GRs: The contents of all general registers are undefined except the following:
• GR20 (bank 1) contains the SALE_ENTRY State Parameter as defined in
Figure
values 3, RECOVERY CHECK, for the first call to SALE_ENTRY, and 0, RESET, for
the second call to SALE_ENTRY are valid.
• GR32 contains 0 indicating that SALE_ENTRY was entered from PALE_RESET.
• GR33 contains information about the geographically significant unique
processor ID, and a mask that indicates which bits in the LID register (CR64)
are read-only. Firmware should write the processor's local interrupt identifier in
the programmable portion of the LID register. Writes to the read-only bits are
ignored. See
Volume 2, Part 1: Processor Abstraction Layer
11-7. For the function field of the SALE_ENTRY State Parameter, only the
Figure 11-8 for the definition of this parameter.
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