Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 292

3.4 Processor Virtualization
Processors in the Itanium Processor Family may optionally implement a mechanism to
support processor virtualization. This includes an additional PSR.vm bit (see
3.3.2, "Processor Status Register
take a Virtualization fault (see
vector (0x6100)" on page
The set of instructions which are virtualized by PSR.vm are listed in
Table 3-10.
All privileged instructions
Some non-privileged
instructions (virtualized at
all privilege levels)
Some non-privileged
instructions (virtualized at
privilege level 0)
Reading AR[ITC] or
AR[RUC] with PSR.si==1
(virtualized at all privilege
levels)
Instructions which write
privileged registers
a. Virtualization of the probe instruction is configurable, see
Virtualization" on page 2:344
Processors which support processor virtualization must provide an
implementation-dependent mechanism for disabling the vmsw instruction. When
enabled, the vmsw instruction functions as described on the vmsw instruction page.
When disabled, the vmsw instruction always raises a Virtualization fault when executed
at the most privileged level.
Processors which support processor virtualization may provide an
implementation-dependent mechanism to disable virtual machine features, see
"PAL_PROC_GET_FEATURES – Get Processor Dependent Features (17)" on page 2:446
for details.
Processor virtualization is largely invisible to system software, and therefore its effects
on virtualized instructions are not discussed in this document, except on the instruction
description pages themselves.
2:44
Section 5.6, "Interruption Priorities"
2:209).
Virtualized Instructions
Class
itc.i, itc.d, itr.i, itr.d, ptc.l, ptc.g, ptc.ga, ptc.e, ptr,
tak, tpa, mov rr, mov pkr, mov cr, mov ibr, mov dbr, mov pmc,
mov to pmd, ssm, rsm, mov psr, rfi, bsw
thash, ttag, mov from cpuid, probe
cover, probe
mov from ar.itc, mov from ar.ruc
mov to ar.itc, mov to ar.ruc
for details.
(PSR)"), which, when 1, causes certain instructions to
Virtualized Instructions
a
Section 11.7.4.2.8, "Probe Instruction
§
Volume 2, Part 1: System State and Programming Model
Section
and "Virtualization
Table 3-10 below.
a