Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 409

If control register bit PMV.m is one, a performance monitoring interrupt is disabled from
being pended. When PMV.m is zero, the interruption is received and held pending.
(Further masking by the PSR.i, TPR and in-service masking can keep the interrupt from
being raised.)
Implementation dependent PMD registers (0-3) cannot report events in the overflow
registers; those 4 bit positions are used for other purposes.
Figure 7-6.
63
Under frozen count conditions when PMC[0].fr is one (either by a performance counter
overflow, or an explicit software write and serialization), the processor suspends all
event monitoring, i.e. counters do not increment and overflow bits as well as
model-specific monitoring are frozen. Normal counting conditions are restored by
software writing a zero to the freeze bit and serializing to resume event monitoring.
When the freeze bit is in-flight, whether counters count events and reads return
non-decreasing values is implementation dependent. Instruction serialization is
required to ensure that the behavior specified by PMC[0].fr is observed.
Table 7-7.
Register
PMC[0]
PMC[0]
PMC[0]..PMC[3]
Volume 2, Part 1: Debugging and Performance Monitoring
Figure 7-6 shows the Performance Monitor Overflow Status registers.
Performance Monitor Overflow Status Registers
(PMC[0]..PMC[3])
overflow
Performance Monitor Overflow Register Fields
(PMC[0]...PMC[3])
Field Bits
fr 0
ig 3:1
overflow implemented
monitors
unimplemented
monitors
60
overflow
overflow
overflow
Performance Monitor "freeze" bit. This bit is volatile
state, i.e., it is set by the processor whenever:
• a generic performance monitor overflow occurs
and its overflow interrupt bit (PMC[n].oi) is set
to one.
• a model-specific performance monitor signals
an interrupt.
The freeze bit can also be set by software to enable or
disable all event monitoring.
If the freeze bit is one, event monitoring is disabled.
If the freeze bit is zero, event monitoring is enabled.
If the freeze bit is in-flight, event monitoring behavior is
implementation dependent.
Ignored
Bit vector indicating which performance monitor
overflowed. Overflow status bits are sticky, they are set
to 1 by the processor if the corresponding PMD
overflows; otherwise they are left unchanged. Multiple
overflow status bits may be set, independent of
whether counter overflow causes an interrupt or not.
Ignored
4 3 2 1
ig
3
Description
2:161
0
fr
1