Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 277

a. User mask bits are implicitly serialized if accessed via user mask instructions; sum, rum, and move to User
Mask. If modified with system mask instructions; rsm, ssm and move to PSR.l, software must explicitly
serialize to ensure side effects are observed before dependent instructions.
b. User mask modification serialization is implicit only for monitoring data execution events. Software should
issue instruction serialization operations before monitoring instruction events to achieve better accuracy.
c. Requires instruction serialization to guarantee that VHPT walks initiated on behalf of an instruction reference
observe the new value of this bit. Otherwise, data serialization is sufficient to guarantee that the new value is
observed.
d. The effect of masking external interrupts with rsm is observed by the next instruction. However, the processor
does not ensure unmasking interruptions with ssm is immediately observed. Software can issue a data
serialization operation to ensure the effects of setting PSR.i are observed before a given point in program
execution.
e. Requires instruction or data serialization, based on whether the dependent "use" is an instruction fetch access
or data access.
f. CPL can be modified due to interruptions, Return From Interruption (rfi), Enter Privilege Code (epc), and
Branch Return (br.ret) instructions.
g. Can only be modified by the Return From Interruption (rfi) instruction. rfi performs an explicit instruction
and data serialization operation.
h. Modification of the PSR.is bit by a br.ia instruction set is implicitly instruction serialized.
i. PSR.mc is set to 1 after a machine check abort or INIT; otherwise, unmodified on interruptions.
j. After an interruption this bit is normally unchanged, however after a PAL-based interruption this bit is set to 0.
k. This bit is set to 0 after the successful execution of each instruction in a bundle except for rfi which may set
it to 1.
l. This bit is ignored when restarting IA-32 instructions and set to zero when br.ia or rfi successfully
complete and before the first IA-32 instruction starts execution.
m. After an interruption, rfi, or bsw the processor ensures register accesses are made to the new register bank.
For interruptions, rfi and bsw, the processor ensures all register accesses and outstanding loads prior to the
bank switch operate on the prior register bank.
n. Can be modified by the Return From Interruption (rfi) and Virtual Machine Switch (vmsw) instructions. rfi
performs an explicit instruction and data serialization operation. Modification of PSR.vm bit by the vmsw
instruction is implicitly serialized.
3.3.3 Control Registers
Table 3-3
requirements to ensure side effects are observed by subsequent instructions. However,
reads of a control register must be data serialized with prior writes to the same register.
The serialization required column only refers to the side effects of the data value.
Writes to read-only registers (IVR, IRR0-3) result in an Illegal Operation fault, accesses
to reserved registers result in a Illegal Operation fault. Accesses can only be performed
by mov to/from instructions defined in
Privileged Operation fault is raised.
Table 3-3.
Global
Control
Registers
Volume 2, Part 1: System State and Programming Model
defines all registers in the control register name space along with serialization
Control Registers
Register Name
CR0 DCR
CR1 ITM
CR2 IVA
CR3
CR4 ITO
CR5-7
CR8 PTA
CR9-15
Table 3-4 at privilege level 0; otherwise, a
Description
Default Control Register
Interval Timer Match register
Interruption Vector Address
reserved
Interval Timer Offset Register
reserved
Page Table Address
reserved
Serialization
Required
inst/data
a
data
a
inst
a
data
b
inst/data
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