Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 856

10.5.1 Notation
Preprocessor macros for function ENTRY and END are used in the examples to reduce
duplication of code and reduce document space requirements.
#define ENTRY(label) \
.text; \
.align 32;; \
.global label; \
.proc label; \
label::
#define END(label) .endp
10.5.2 TPR and XPTR Usage Example
This code will allow certain interrupts to be masked by increasing/decreasing the task
priority register. If you don't want to mask all external interrupts, you can raise the
priority level to mask out only the interrupts that have higher priority (and no effect on
your current critical section).
We also take the expensive route here by updating not only the processor TPR, but the
External Task Priority Register used by the chipset (if supported) as a hint to what
processor should receive the next external interrupt.
//
// routine to set the task priority register to mask
// interrupts at the specific level or below
//
// INPUT: SPL level
//
TPR_MIC=4
TPR_MIC_LEN=4
.global external_task_pri_reg// address points to Interrupt Delivery block
ENTRY(set_spl)
alloc r18=ar.pfs,1,0,0,0
dep.z r22=r32,TPR_MIC,TPR_MIC_LEN
movl r19=external_task_pri_reg
;;
mov cr.tpr=r22
ld8 r20=[r19]
;;
srlz.d
immediately
st1 [r20]=r32
(XTP)
br.ret.sptk b0
;;
END(set_spl)
2:608
// get address of EXt. TASK Priority Register
// srlz.d only required if want TPR update effective
// if supported by platform: update eXternal Task Priority
Volume 2, Part 2: External Interrupt Architecture