Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 664

PAL_MC_ERROR_INFO
Table 11-91. tlb_check Fields (Continued)
Field
rv
level
reserved
dtr
itr
dtc
itc
op
reserved
hlth
reserved
is
iv
pl
pv
mcc
tv
rq
rp
pi
a. Hardware is tracking the operating status of the structure type and level reporting the error. The hardware
reports a "normal" status when the number of entries within a structure reporting repeated corrections is at or
below a pre-defined threshold. A "cautionary" status is reported when the number of affected entries exceeds
a pre-defined threshold.
2:416
Bits
9 Reserved
11:10 The level of the TLB where the error occurred. A value of 0 indicates the first level of TLB
15:12 Reserved
16 Error occurred in the data translation registers
17 Error occurred in the instruction translation registers
18 Error occurred in data translation cache
19 Error occurred in the instruction translation cache
23:20 Type of cache operation that caused the machine check:
0 – unknown
1 – TLB access due to load instruction
2 – TLB access due to store instruction
3 – TLB access due to instruction fetch or instruction prefetch
4 – TLB access due to data prefetch (both hardware and software)
5 – TLB shoot down access
6 – TLB probe instruction (probe, tpa)
7 – move in (VHPT fill)
8 – purge (insert operation that purges entries or a TLB purge instruction)
All other values are reserved.
29:24 Reserved
31:30 Health indicator. This field will report if the tlb type and level reporting this error supports
hardware status tracking and the current status of this tlb.
00 – No hardware status tracking is provided for the tlb type and level reporting this
event.
01 – Status tracking is provided for this tlb type and level and the current status is
a
normal.
10 – Status tracking is provided for the tlb type and level and the current status is
a
cautionary. When a tlb reports a cautionary status the "hardware damage" bit of the
PSP (see Figure 11-11, "Processor State Parameter," on page
11 – Reserved
53:32 Reserved
54 Instruction set. If this value is set to zero, the instruction that generated the machine
check was an Intel Itanium instruction. If this bit is set to one, the instruction that
generated the machine check was IA-32 instruction.
55 The is field in the TLB_check parameter is valid.
57:56 Privilege level. The privilege level of the instruction bundle responsible for generating the
machine check.
58 The pl field of the TLB_check parameter is valid.
59 Machine check corrected: This bit is set to one to indicate that the machine check has
been corrected.
60 Target address is valid: This bit is set to one to indicate that a valid target address has
been logged.
61 Requester identifier: This bit is set to one to indicate that a valid requester identifier has
been logged.
62 Responder identifier: This bit is set to one to indicate that a valid responder identifier has
been logged.
63 Precise instruction pointer. This bit is set to one to indicate that a valid precise instruction
pointer has been logged.
Description
2:299) will be set as well.
Volume 2, Part 1: Processor Abstraction Layer