Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 490

Table 10-2.
Field
base
lim
stype
s
dpl
p
ig
g
System segment selectors and descriptors for GDT and LDT are maintained in Itanium
general registers to support segment register loads used extensively by segmented
16-bit code. On the transition into the IA-32 instruction set, GDT/LDT descriptor table
must be initialized if IA-32 code will perform protected mode segment register loads or
far control transfers.
Within the IA-32 System Environment, GDT and LDT are considered privileged
operating system segmentation resources. However, in the Itanium System
Environment, applications can transition between the IA-32 and Itanium instruction set
and bypass IA-32 segmentation. Itanium user level instructions can also directly modify
all selectors and descriptors including GDT and LDT. An operating system should either
protect memory with virtual memory management mechanisms defined by the Itanium
architecture or disabled application level instruction set transitions. Within the Itanium
System Environment, GDT/LDT memory spaces must be mapped into user space, since
supervisor overrides for accesses to GDT/LDT are disabled.
The TSSD descriptor points to the I/O Permission Bitmap. If CFLG.io is 1, IN, INS, OUT,
and OUTS consult the TSSD I/O permission bitmap as defined in the Intel
IA-32 Architectures Software Developer's Manual. If CFLG.io is 0, the TSSD I/O
permission bitmap is not checked. See
on I/O port permission and for TLB-based access control. The TSSD register is not used
within the Itanium System Environment to support task switches, or interlevel control
transfers. If the TSSD is used for I/O Permissions, Itanium architecture-based
operating system software must ensure that a valid 286 or 386 Task State Descriptor is
loaded, otherwise IN/OUT operations to the TSSD I/O permission bitmap will result in
undefined behavior.
The IDT descriptor is not supported or defined within the Itanium System Environment.
2:242 Volume 2, Part 1: Itanium
IA-32 System Segment Register Fields (LDT, GDT, TSS)
Bits
31:0 Segment Base value. This value when zero extended to 64-bits, points to the start of the
segment in the 64-bit virtual address space for IA-32 instruction set memory references.
This value is ignored for Intel Itanium instruction set memory references.
51:32 Segment Limit. Contains the maximum effective address value within the segment. See the
®
Intel 64 and IA-32 Architectures Software Developer's Manual for details and segment
limit fault conditions.
55:52 Segment Type identifier. See the Intel
Manual for encodings and definition.
56 Non System Segment. If 1, a data segment, if 0 a system segment.
58:57 Descriptor Privilege Level. The DPL is checked for memory access permission for IA-32
instruction set memory references.
59 Segment Present bit. If 0, and an IA-32 memory reference uses this segment an
IA_Exception(GPFault) is generated.
62:60 Ignored – For the LDT/GDT/TSS descriptors reads of this field return the last value written
by Itanium architecture-based code. Reads of this field return zero if written by IA-32
descriptor loads.This field is ignored by the processor during IA-32 instruction set execution.
This field may have a future use and should be set to zero by software.
63 Segment Limit Granularity. If 1, scales the segment limit by lim=(lim<<12) | 0xFFF for IA-32
instruction set memory references.
®
Architecture-based Operating System Interaction Model with IA-32 Applications
Description
®
64 and IA-32 Architectures Software Developer's
Section 10.7, "I/O Port Space Model"
®
64 and
for details