Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 789

A processor based on the Itanium architecture provides the following interruption
registers for collecting information about the latest interruption or the state of the
machine at the time of the interruption:
• IPSR – A copy of the processor status register (PSR) at the moment the
interruption occurred. The OS can use the IPSR to determine the value of any PSR
bit when the interruption occurred. The contents of IPSR are restored into the PSR
when the OS executes an rfi instruction. If the OS wishes to change the PSR state
of the interrupted process (e.g. to step over an instruction debug fault), it can do so
by modifying the IPSR contents before executing the rfi. When an interruption
occurs, the processor sets IPSR.ri to the slot number (0, 1, or 2) of the instruction
that was interrupted.
• IIP – A copy of the instruction pointer (IP) where the interruption occurred. The
instruction bundle address contained in IIP, along with the IPSR.ri field, defines the
instruction whose execution was interrupted. This instruction has not completed
(i.e. it has not retired), so when the OS returns to the interrupted context, typically
this is the instruction at which execution of the interrupted context resumes
the OS executes an rfi instruction, the contents of IIP are copied into the IP
register and the processor begins fetching instructions from this address.
• ISR – Contains extra information about the specific interruption that occurred. This
register is useful for determining exactly which interruption occurred for
interruptions which share the same IVT vector.
• IFA – Faults related to addressing (e.g. Data TLB fault) materialize the faulting
address in this register.
• ITIR – Faults related to addressing materialize the default page size and permission
key for the region to which the faulting address belongs in this register.
• IIPA – Contains the instruction bundle address of the last instruction to retire
successfully while PSR.ic was 1. In conjunction with ISR.ei, IIPA can be used by
software to locate the instruction that caused a trap or that was executed
successfully prior to a fault or interrupt.
• IIM – Instructions that take a Speculation fault (e.g. chk) or a Break Instruction
fault (e.g. break.i) write this register with their immediate field when taking these
faults. For these cases, the IIM register can be used to emulate the instruction, or
to pass information to the fault handler; for example, software can use a particular
immediate field value in a break instruction to indicate to the operating system that
a system call is being performed.
• IHA – Faults related to the VHPT place the VHPT hash address in this register. See
Section 5.3, "Virtual Hash Page Table" on page 2:571
• IFS – This register can be used by software to save a copy of the interrupted
context's PFS register, but an interruption handler must do this explicitly; hardware
only clears the valid bit (IFS.v) upon interruption. See below for details.
• IIB0, IIB1 – Contain the 16-byte instruction bundle related to the interruption. Note
that the IIB registers do not provide bundle information for all interruptions and are
not supported on all processor implementations; please refer to
1. When an instruction faults because it requires emulation by the OS, the OS will normally skip the
emulated instruction by returning to the instruction bundle address and slot number that follows IIP
in program order. It does so by writing the next in-order bundle address and slot number into IIP and
IPSR.ri, respectively, before executing an rfi instruction. Details on emulation handlers is in
Chapter 7, "Instruction Emulation and Other Fault Handlers."
Volume 2, Part 2: Interruptions and Serialization
1
. When
for details.
Chapter 8,
2:541