Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 823

5.4.2 VHPT Translation Vector
Processors based on the Itanium architecture does not perform recursive TLB hardware
page walks. Since the VHPT is itself a virtually addressed structure, each reference
performed by the walker itself goes through the TLBs and may miss. These faults are
raised when the VHPT walker is enabled, but the walker misses the TLBs when
attempting to service a TLB miss caused by the program.
There is a separate vector for each fault type (data and instruction).
Upon entry to this fault handler, the IHA, IFA, and ITIR control registers are initialized
by the hardware as follows:
• IHA – contains the virtual address of the hashed page table address corresponding
to the reference which raised the fault.
• ITIR – contains the default translation information for the VHPT address which
missed the TLBs (i.e. for the virtual address contained in IHA). The access key field
is set to the region ID from the RR corresponding to the VHPT address. The page
size field is set to the preferred page size (RR.ps) from the RR corresponding to the
VHPT address.
• IFA – contains the original faulting address that the VHPT walker was attempting to
resolve.
The fault handler for a short format VHPT performs the following steps, at a minimum,
to handle the fault:
1. Move the IHA register into a general register.
2. Perform a thash instruction using the general register from step 1 This will
produce, in the target register, the VHPT address of the VHPT entry that maps the
VHPT entry corresponding to the original faulting address (i.e. the address in
IFA).
3. Using the target general register of the thash from step 2 as the load address,
perform an 8-byte load from the VHPT. Note that the format of these first 8 bytes
is identical to the format required for TLB insertion. Software must be prepared to
take a nested TLB fault if this load misses the TLBs.
4. Move the IHA value from the general register written in step 1 into the IFA
register.
5. Using the general register from step 3 that holds the contents of the VHPT entry,
perform a data TC insert using the itc.d instruction. (VHPT references always go
through the data TLBs.)
6. In an MP environment, reload the VHPT entry from step 3 into a different general
register and compare the value to the one loaded in step 3. If the values are not
the same, then the VHPT has been modified by another processor between steps
3 and 4, and the entry will have to be re-inserted. In this case, purge the entry
just inserted using a ptc.l instruction. The fault will re-occur after the rfi in
step 7 (unless the VHPT walker succeeds on the next TLB miss) and the fault
handler will re-attempt the insertion. (Uniprocessor environments may skip this
step.)
7. rfi.
Volume 2, Part 2: Memory Management 2:575