Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 434
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External Interrupt vector (0x3000)
Name
Cause
There are unmasked external interrupts pending from external devices, other
processors, or internal processor events and:
• PSR.i is 1, while executing Itanium instructions
• PSR.i is 1 and (CFLAG.if is 0 or EFLAG.if is 1), while executing IA-32 instructions
IPSR.is indicates which instruction set was executing at the time of the interruption.
Interruptions on this vector:
External Interrupt
Parameters
IIP, IPSR, IIPA, IFS – are defined; refer to
IVR – Highest priority unmasked pending external interrupt vector number. If there are
no unmasked pending interrupts the "spurious" interrupt vector (15) is reported.
IIB0, IIB1 – If implemented, the IIB registers are undefined. Please refer to
Section 3.3.5.10, "Interruption Instruction Bundle Registers (IIB0-1 – CR26, 27)" on
page 2:42
ISR – The ISR.ei bits are set to indicate which instruction was to be executed when the
external interrupt event was taken. The defined ISR bits are specified below. For
external interrupts taken in the IA-32 instruction set, ISR.ei, ni and ir bits are 0.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Software is expected to avoid situations which could cause ISR.ni to be 1.
Notes:
2:186
for details on the IIB registers.
0
0
0
page 2:165
for a detailed description.
8
0
0
ei
0 ni ir 0 0 0 0 0 0
Volume 2, Part 1: Interruption Vector Descriptions
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