Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 449
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Unaligned Reference vector (0x5a00)
Name
Cause
If PSR.ac is 1, and the data address being referenced by an Itanium instruction is not
aligned to the natural size of the load, store, or semaphore operation, or a data
reference is made to a misaligned datum not supported by the implementation.
"Memory Access Instructions" on page 1:57.
IA_32_Exception(Alignment Check) fault is raised; see
Vector Descriptions."
are delivered on the IA_32_Exception(Alignment_Check) vector.
If the data reference specified is both unaligned to the natural datum size and
unsupported, then an Unaligned Data Reference fault is taken.
Interruptions on this vector:
Unaligned Data Reference fault
Parameters
IIP, IPSR, IIPA, IFS – are defined; refer to
IFA – The address of the data being referenced.
IIB0, IIB1 – If implemented, the IIB registers contain the instruction bundle pointed to
by IIP. Please refer to
(IIB0-1 – CR26, 27)" on page 2:42
ISR – The value for the ISR bits depend on the type of access performed and are
specified below.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Volume 2, Part 1: Interruption Vector Descriptions
IA-32 instructions can not raise this fault, IA-32 unaligned events
Section 3.3.5.10, "Interruption Instruction Bundle Registers
0
0
0
For IA-32 data memory references, an
Chapter 9, "IA-32 Interruption
page 2:165
for a detailed description.
for details on the IIB registers.
ed
See
8
7
6
5
4
3
2
0
ei
0 ni 0 0 sp 0
r w 0
1
0
2:201
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