Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 489

Table 10-1.
®
Intel
Itanium
Reg
LID, IVR,
TPR, EOI,
IRR0, IRR1,
IRR2, IRR3,
ITV, PMV,
LRR0, LRR1,
CMCV
Translation Resources
TRs
TCs
RRs
PKRs
Debug Registers
IBRs
DBRs
Performance Monitors
PMCs
PMDs
a. IA-32 MOV from CR0 and CR4 return the value in the CFLG register.
b. The IOBase register is used by IN/OUT instructions. If IN/OUT operations are disabled via CFLG.io, this
register can be used for other values.
c. The TSSD registers are used by IN/OUT instructions for I/O permission via CFLG.io. If access to the TSS is
disabled, these registers can be used for other values.
d. The Mov from CR2,CR3 instructions return the value contained in KR2.
10.3 IA-32 System Segment Registers
System Descriptors are maintained in an unscrambled format shown in
differs from the IA-32 scrambled memory descriptor format. The unscrambled register
format is designed to support fast conversion of IA-32 segmented 16/32-bit pointers
into virtual addresses by Itanium architecture-based code. IA-32 segment register load
instructions unscramble the GDT/LDT memory format into the descriptor register
format on a segment register load. Itanium architecture-based software can also
directly load descriptor registers provided they are properly unscrambled by software.
When Itanium architecture-based software loads these registers, no data integrity
checks are performed at that time if illegal values are loaded in any fields. For a
complete definition of all bit fields and field semantics refer to the Intel
IA-32 Architectures Software Developer's Manual.
Figure 10-1.
63 62
g ig
®
Volume 2, Part 1: Itanium Architecture-based Operating System Interaction Model with IA-32 Applications
IA-32 System Register Mapping (Continued)
®
IA-32 Reg Convention
shared
shared
dr0-3, dr7 shared
dr0-3, dr7
shared
shared
IA-32 System Segment Register Descriptor Format (LDT, GDT,
TSS)
60 59 58 57 56 55 52 51
p dpl s stype
Size
Intel Itanium external interrupt control registers are used
to generate, prioritize and delivery external interrupts
during IA-32 or Intel Itanium instruction set execution.
64
All Intel Itanium virtual memory registers can be used for
memory references (including IA-32).
64 Intel Itanium debug registers are used memory
references (including IA-32).
64 Intel Itanium performance monitors measure
performance events (including IA-32).
64 reflect performance monitor results of execution
(including IA-32)
32 31
lim{19:0}
Description
Figure 10-1
®
64 and
base{31:0}
that
0
2:241