Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 383

The RSE operates concurrently and asynchronously with respect to instruction
execution by taking advantage of unused memory bandwidth to dynamically perform
register spill and fill operations. The algorithm employed by the RSE to determine
whether and when to spill/fill is implementation dependent. Software can not depend
on the spill/fill algorithm. To ensure that the processor and RSE activities do not
interfere with each other, software should not access stacked registers outside of the
current stack frame. The architecture guarantees register stack integrity by faulting on
writes to out-of-frame registers. Reads from out-of-frame registers may interact with
RSE operations and return undefined data values. However, out-of-frame reads are
required to propagate NaT bits.
The operation of the RSE is controlled by the Register Stack Configuration (RSC)
application register. Activity between the processor and the RSE is synchronized only
when alloc, flushrs, loadrs, br.ret, or rfi instructions actually require registers to
be spilled or filled, or when software explicitly requests RSE synchronization by
executing a mov to/from RSC, BSPSTORE or RNAT application register instruction.
6.2 RSE Internal State
Table 6-1
The RSE internal state elements described here are not directly exposed to the
programmer as architecturally visible registers. As a consequence, RSE internal state
does not need to be preserved across context switches or interruptions. Instead, it is
modified as the side-effect of register stack-related instructions. To describe the effects
of these instructions a complete definition of the RSE internal state is essential. To
distinguish them from architecturally visible resources, all RSE internal state elements
are prefixed with "RSE." Other RSE related resources are architecturally visible and are
exposed to software as application registers: RSC, BSP, BSPSTORE, and RNAT.
Table 6-1.
RSE.N_STACKED_PHYS
RSE.BOF
RSE.StoreReg
RSE.LoadReg
RSE.BspLoad
RSE.RNATBitIndex
RSE.CFLE
Volume 2, Part 1: Register Stack Engine
describes architectural state that is maintained by the register stack engine.
RSE Internal State
Name
Number of Stacked Physical registers:
Implementation dependent size of the stacked
physical register file.
Bottom-of-frame register number: Physical
register number of GR32.
RSE Store Register number: Physical register
number of next register to be stored by RSE.
RSE Load Register number: Physical register
number one greater than the next register to
load (modulo the number of stacked physical
registers).
Backing Store Pointer for memory loads: 64-bit
Backing Store Address 8 bytes greater than the
next address to be loaded by the RSE.
RSE NaT Collection Bit Index: 6-bit wide RNAT
Collection Bit Index (defines which RNAT
collection bit gets updated)
RSE Current FrameLoad Enable: Control bit
that permits the RSE to load registers in the
current frame after a br.ret or rfi.
Description Corresponds To
AR[BSP]
AR[BSPSTORE]
RSE.BspLoad
RSE.BspLoad
AR[BSPSTORE]{8:3}
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