Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 793

4. Allocate a "trap frame" to store the interrupted context's state on the kernel
memory stack, and move the interruption state (IIP, IPSR, IIPA, ISR, IFA, IFS,
IIB0-1), the interrupted memory stack pointer and the interrupted predicate
registers from the banked registers to the trap frame.
5. Save register stack and RSE state by following the steps outlined in
Section 6.11.1, "Switch from Interrupted Context" on page
a. If IPSR.cpl is zero and the interrupted context was not executing on a kernel
Otherwise, the interrupted context was already executing on the kernel backing
store. In this case, no new BSPSTORE pointer needs to be setup. The sequence in
Section 6.11.1, "Switch from Interrupted Context" on page
required, however, step 6 in that sequence can be omitted.
In either case, the interrupted register stack and RSE state (RSC, PFS, IFS,
BSPSTORE, RNAT, and BSP) needs to be preserved, and should be saved either to
the trap frame on the kernel memory stack, or to a newly allocated register stack
frame.
6. Switch banked register to bank one and re-enable interruption collection as
follows:
With interruptions collection re-enabled, the kernel may now branch to paged
code and may reference paged data structures.
7. Preserve branch register and application register state according to operating
system conventions.
8. Preserve general and floating-point register state. If this is an involuntary
interruption, e.g. an external interrupt or an exception, then software must save
the interrupted context's volatile general register state (scratch registers) to the
"trap frame" on the kernel memory stack, or to the newly allocated register stack
frame. If this is a voluntary system call then there is no volatile register state.
Preserved registers may or may not be spilled depending on operating system
conventions. Additionally, the Itanium architecture provides mechanisms to
reduce the amount of floating-point register spills and fills. More details on
preservation of register context are given in
State in the OS" on page
9. At this point enough context has been saved to allow complete restoration of the
interrupted context. Re-enable taking of external interrupts using the ssm
instruction as follows:
Volume 2, Part 2: Interruptions and Serialization
backing store (determined by inspecting BSPSTORE), then the new kernel
BSPSTORE needs to be allocated such that enough space is provided for the
RSE to spill all stacked registers. The architectural required maximum RSE
spill area is 16KBytes. As a result, BSPSTORE should be offset from the base
of the kernel backing store base by at least 16KBytes. This offset can be
reduced if the kernel queries PAL for the actual implementation-specific
number of stacked physical registers (RSE.N_STACK_PHYS). Based on
RSE.N_STACK_PHYS, the required minimum offset in bytes is:
8 * (RSE.N_STACK_PHYS + 1 + truncate((RSE.N_STACK_PHYS + 62)/63))
ssm 0x2000 // Set PSR.ic
bsw.1;; // Switch to register bank 1
srlz.d // Serialize PSR.ic update
2:551.
2:148.
2:148, is still
Section 4.2, "Preserving Register
2:545