Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 572

Figure 11-12. Interaction of P-states with HALT State
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pf
pf
pf
As shown above, the value returned for performance_index does not account for the
performance during the time spent by the logical processor in the HALT state. This
provides for better accuracy in the value reported for performance_index, allowing the
caller to make optimal adjustments to the system utilization even in scenarios where
we have interactions between P-states and HALT state.
11.7 PAL Virtualization Support
This section describes the PAL architectural support for Itanium processor virtualization.
On processors in the Itanium Processor Family that support processor virtualization, the
PAL virtualization support described in this document will be available. Itanium
processor virtualization support can be determined by calling
PAL_PROC_GET_FEATURES.
The virtualization support in PAL presents an implementation-independent interface to
enable the VMM to implement software policies to manage/support virtualization of
Itanium processors.
The PAL extensions for virtualization consist of three main components:
1. A set of procedures to support virtualization operations. These procedures allow
the VMM to configure logical processors for virtualization operations and
suspend/resume virtual processors on logical processors. Details for this
component are described in
2. A set of services to provide low-latency, low-overhead support for
performance-critical VMM operations. Details for this component are described in
Section 11.11, "PAL Virtualization Services" on page
3. A PAL intercept interface to allow PAL to deliver virtualization events to the VMM
in a low-latency, low-overhead manner. This PAL-to-VMM interface also allows
PAL to provide optimizations for VMM operations. Details for this component are
described in
page
2:324
Performance
(P0)
0
(P1)
1
(P2)
2
Enter HALT State
(P3)
3
t t
0 1
(Previous) GET SET(P3)
Section 11.7.3, "PAL Intercepts in Virtual Environment" on
2:332.
Exit HALT State
t
h1
Section 11.10, "PAL Procedures" on page
Volume 2, Part 1: Processor Abstraction Layer
t t
h2 2
(Current) GET
2:353.
2:486.
Time