Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 391

Table 6-5.
Affected State
AR[BSP]{63:3}
AR[BSPSTORE]{63:3}
RSE.BspLoad{63:3}
AR[RNAT]
RSE.RNATBitIndex
CR[IFS]
CFM
a. These instructions have undefined behavior with an incomplete frame.
Register Frame" on page 2:146.
b. In general, eager RSE implementations will preserve RSE.BspLoad during a flushrs. Lazy RSE
implementations may set RSE.BspLoad to AR[BSPSTORE] after flushrs completes or faults.
By specifying a zero RSC.loadrs value loadrs can be used to invalidate all stacked
registers outside the current frame. loadrs causes the contents of the RNAT register to
become undefined. The NaT collection index is set to bits {8:3} of the new BSPSTORE.
A loadrs instruction must be the first instruction in an instruction group otherwise the
results are undefined. The following conditions cause loadrs to raise an Illegal
Operation fault:
• If RSC.mode is non-zero.
• If both CFM.sof and RSC.loadrs are non-zero.
• If RSC.loadrs specifies more words to be loaded than will fit in the stacked physical
register file (RSE.N_STACKED_PHYS).
6.5.5 Bad PFS used by Branch Return
On a br.ret, if the PFS application register defines an output area which is larger than
the number of implemented stacked registers minus the size of dirty partition
((AR[PFS].sof - AR[PFS].sol) > (RSE.N_STACKED_PHYS - RSE.ndirty)), the return will
not restore CFM with AR[PFS].pfm (normal behavior); instead, the return sets all fields
in the CFM (of the procedure being returned to) to zero.
Typical procedure call and return sequences that preserve PFS values and that do not
use cover or loadrs instructions will not encounter this situation.
The RSE will detect the above condition on a br.ret, and update its state as follows:
• The register rename base (RSE.BOF), AR[BSP], and AR[BSPSTORE] are updated as
required by the return.
Volume 2, Part 1: Register Stack Engine
RSE Control Instructions
cover
AR[BSP]{63:3}+ CFM.sof +
(AR[BSP]{8:3} + CFM.sof)/63
Unchanged
Unchanged
Unchanged
Unchanged
if (PSR.ic == 0) {
CR[IFS].ifm = CFM
CR[IFS].v = 1}
CFM.sof = 0
CFM.sol = 0
CFM.sor = 0
CFM.rrb.gr = 0
CFM.rrb.fr = 0
CFM.rrb.pr = 0
Instruction
a
flushrs
Unchanged Unchanged
AR[BSP]{63:3} AR[BSP]{63:3} -
AR[RSC].loadrs{13:3}
b
Model specific AR[BSP]{63:3} -
AR[RSC].loadrs{13:3}
Updated UNDEFINED
AR[BSPSTORE]{8:3} AR[BSPSTORE]{8:3}
Unchanged Unchanged
Unchanged Unchanged
See "RSE Behavior with an Incomplete
a
loadrs
2:143