Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 503

Table 10-5.
IA-32 Instruction
CMPXCHG, 8B
CPUID
CWD, CDQ
CVTPI2PS, CVTPS2PI,
CVTSI2SS, CVTSS2SI,
CVTTPS2PI, CVTTSS2SI
DAA, DAS
DEC
DIV
DIVPS, DIVSS
ENTER
EMMS
®
Volume 2, Part 1: Itanium Architecture-based Operating System Interaction Model with IA-32 Applications
IA-32 Instruction Summary (Continued)
® ®
Intel Itanium System
Environment
Optional Lock Intercept
unchanged
Comments
If Locks are disabled (DCR.lc is 1) and a processor
external lock transaction is required
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