Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 616

PAL_BUS_GET_FEATURES
Table 11-63. Processor Bus Features
Bits Class
63 Opt.
62 Opt.
61 Opt.
60 Opt.
59 Opt.
58 Opt.
57 Opt.
56 Opt.
55 Opt.
54 Opt.
53 Opt.
52 Opt.
51:32 N/A
31 Opt.
30 Opt.
29 Opt.
28:0 N/A
2:368
Control
Req. Disable Bus Data Error Checking. When 0, bus data errors are detected and
single bit errors are corrected. When 1, no error detection or correction is done.
Req. Disable Bus Address Error Signalling. When 0, bus address errors are signalled
on the bus. When 1, no bus errors are signalled on the bus. If Disable Bus
Address Error Checking is 1, this bit is ignored.
Req. Disable Bus Address Error Checking. When 0, bus errors are detected, single
bit errors are corrected., and a CMCI or MCA is generated internally to the
processor. When 1, no bus address errors are detected or corrected.
Req. Disable Bus Initialization Event Signaling. When 0, bus protocol errors (BINIT#)
are signaled by the processor on the bus. When 1, bus protocol errors (BINIT#)
are not signaled on the bus. If Disable Bus Initialization Event Checking is 1,
this bit is ignored.
Req. Disable Bus Initialization Event Checking. When 0, bus protocol errors (BINIT#)
are detected and sampled and an MCA is generated internally to the processor.
When 1, the processor will ignore bus protocol error conditions (BINIT#).
Req. Disable Bus Requester Bus Error Signalling. When 0, BERR# is signalled if a
bus error is detected. When 1, bus errors are not signalled on the bus.
Req. Disable Bus Requester Internal Error Signalling. When 0, BERR# is signalled
when internal processor requestor initiated bus errors are detected. When 1,
internal requester bus errors are not signalled on the bus.
Req. Disable Bus Error Checking. When 0, the processor takes an MCA if BERR# is
asserted. When 1, the processor ignores the BERR# signal.
Req. Disable Response Error Checking. When 0, the processor asserts BINIT# if it
detects a parity error on the signals which identify the transactions to which this
is a response. When 1, the processor ignores parity on these signals.
Req. Disable Transaction Queuing. When 0, the in-order transaction queue is limited
only by the number of hardware entries. When 1, the processor's in-order
transactions queue is limited to one entry.
Req. Enable a bus cache line replacement transaction when a cache line in the
exclusive state is replaced from the highest level processor cache and is not
present in the lower level processor caches. When 0, no bus cache line
replacement transaction will be seen on the bus. When 1, bus cache line
replacement transactions will be seen on the bus when the above condition is
detected.
Req. Enable a bus cache line replacement transaction when a cache line in the
shared or exclusive state is replaced from the highest level processor cache
and is not present in the lower level processor caches. When 0, no bus cache
line replacement transaction will be seen on the bus. When 1, bus cache line
replacement transactions will be seen on the bus when the above condition is
detected.
N/A Reserved
Opt. Enable Half transfer rate. When 0, the data bus is configured at the 2x data
transfer rate.When 1, the data bus is configured at the 1x data transfer rate,
Req. Disable Bus Lock Mask. When 0, the processor executes locked transactions
atomically. When 1, the processor masks the bus lock signal and executes
locked transactions as a non-atomic series of transactions.
Req. Request Bus Parking. When 0, the processor will deassert bus request when
finished with each transaction. When 1, the processor will continue to assert
bus request after it has finished, if it was the last agent to own the bus and if
there are no other pending requests.
N/A Reserved
Description
Volume 2, Part 1: Processor Abstraction Layer