Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 791

For example, assume that GR2 contains the new value for IVA and that PSR.i is 1. To
modify the IVA register, software would perform the following code sequence, where
the code page is mapped by an instruction translation register or instruction translation
is disabled:
rsm psr.i
mov cr[iva] = r2
;;
srlz.i
;;
ssm psr.i
3.3.4 Resource Serialization upon rfi
An rfi instruction also performs an instruction and a data serialization operation when
it is executed. Any values that were written to processor register resources by
instructions in an earlier instruction group than the rfi will be observed by the
returned-to instruction, except for those register resources which are also written by
the rfi itself, in which case the value written by the rfi will be observed. This makes
the interruption handler more efficient by avoiding additional data and instruction
serialization operations before returning to the interrupted context.
3.4 Interruption Handling
The Itanium architecture-based operating systems need to distinguish the following
interruption handler types:
• Lightweight interruptions: Lightweight interruption handlers are allocated 1024
bytes (192 instructions) per handler in the IVT. These are discussed in
Section
• Heavyweight interruptions: Heavyweight interruption handlers are allocated only
256 bytes (48 instructions) per handler in the IVT. These are discussed in
Section
• Nested interruptions: If an interruption is taken when PSR.ic was 0 or was in-flight,
a nested interruption occurs. Nested interruptions are discussed in
3.4.1 Lightweight Interruptions
Lightweight interruption handlers are allocated 1024 bytes (192 instructions) per
handler in the IVT. Typically, lightweight handlers are written in Itanium
architecture-based assembly code, and run in their entirety with interruption collection
turned off (PSR.ic = 0) and external interrupts disabled (PSR.i = 0). Because these
lightweight handlers are usually very short and performance-critical, they are intended
to fit entirely in the space allocated to them in the IVT. An example of a lightweight
interruption handler is the Data TLB vector (offset 0x0800). The first 20 vectors in the
IVT, offsets 0x0000 (VHPT Translation vector) through 0x4c00 (reserved), are
lightweight vectors. Typical lightweight handlers deal with instruction, data or VHPT TLB
Misses, protection key miss handling, and page table dirty or access bit updates.
Volume 2, Part 2: Interruptions and Serialization
// external interrupts disabled upon next instruction
// writing IVA requires instruction serialization
// external interrupts will be re-enabled after next srlz
3.4.1.
3.4.2.
Section 3.4.3.
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