Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 590

the virtual processor status register without any intercepts to the VMM; and the last
value written to the vpsr will be returned, unless a fault condition is detected (see
Table 11-35
simply the values of those bits in the PSR of the logical processor, since those bits are
not virtualized.
If this optimization is disabled, execution of a MOV-from-PSR instruction with
PSR.vm==1 results in a virtualization intercept.
Synchronization is required when this optimization is enabled, see
details.
When this optimization is enabled, certain VPD state is accessed, as described in
Table 11-16, "Virtual Processor Descriptor (VPD)" on page
Table 11-34. Synchronization Requirements for MOV-from-PSR Optimization
vpsr{36:35, 31:6}
See Table 11-17, "Virtual Processor
Descriptor (VPD) – VPSR" on
page 2:328
Table 11-35. Interruptions when MOV-from-PSR Optimization is Enabled
MOV-from-PSR
Note: This field cannot be enabled together with the d_psr_i virtualization disable
control (vdc) described in
alization" on page
control, an error will be returned during PAL_VP_CREATE and
PAL_VP_REGISTER. See
nations" on page 2:349
11.7.4.2.5 MOV-from-CPUID Optimization
The MOV-from-CPUID optimization is enabled by the a_from_cpuid bit in the
Virtualization Acceleration Control (vac) field in the VPD. When this optimization is
enabled, software running with PSR.vm==1 will be able to execute MOV-from-CPUID
instruction to read the virtual CPUID registers without any intercepts to the VMM; and
the corresponding VCPUID value from the VPD will be returned, unless a fault condition
is detected (see
If this optimization is disabled, execution of a MOV-from-CPUID instruction with
PSR.vm==1 results in a virtualization intercept.
Synchronization is required when this optimization is enabled, see
details.
When this optimization is enabled, certain VPD state is accessed, as described in
Table 11-16, "Virtual Processor Descriptor (VPD)" on page
2:342
for details). The value returned for the fml, mfh, ac, up and be bits are
VPD Resource
for details.
Instructions
2:348. If this control is enabled together with the d_psr_i
for details.
Table 11-37 for details).
Synchronization Required
Write
Interruptions
When the MOV-from-PSR optimization is enabled, MOV-from-PSR
instructions with PSR.vm==1, may raise the following faults:
• Illegal Operation fault – if the target operand specifies GR 0 or
an out-of-frame stacked register
• Privileged Operation fault – if vpsr.cpl is not zero
Section 11.7.4.3.7, "Disable PSR Interrupt-bit Virtu-
Section 11.7.4.4, "Virtualization Optimization Combi-
Volume 2, Part 1: Processor Abstraction Layer
Table 11-34 for
2:326.
Table 11-36 for
2:326.