Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 406

Table 7-4.
Field
pm
ig
es
implem.
specific
Event collection is controlled by the Performance Monitor Configuration (PMC) registers
and the processor status register (PSR). Four PSR fields (PSR.up, PSR.pp, PSR.cpl and
PSR.sp) and the performance monitor freeze bit (PMC[0].fr) affect the behavior of all
generic performance monitor registers. Finer, per monitor, control of generic
performance monitors is provided by two PMC register fields (PMC[i].plm, PMC[i].pm).
Event collection for a generic monitor is enabled under the following constraints:
• Generic Monitor Enable[i] =(not PMC[0].fr) and PMC[i].plm[PSR.cpl] and
((not (PMC[i].pm) and PSR.up) or (PMC[i].pm and PSR.pp))
Generic performance monitor data registers (PMD[i]) can be configured to be user
readable (useful for user level sampling and tracing user level processes) by setting the
PMC[i].pm bit to 0. All user-configured monitors can be started and stopped
synchronously by the user mask instructions (rum and sum) by altering PSR.up.
User-configured monitors can be secured by setting PSR.sp to 1. A user-configured
secured monitor continues to collect performance values; however, reads of PMD, by
non-privileged code, return zeros until the monitor is unsecured.
Monitors configured as privileged (PMC[i].pm is 1) are accessible only at privilege level
0; otherwise, reads return zeros. All privileged monitors can be started and stopped
synchronously by the system mask instructions (rsm and ssm) by altering PSR.pp.
Table 7-5
registers.
Updates to generic PMC registers and PSR bits (up, pp, is, sp, cpl) require implicit or
explicit data serialization prior to accessing an affected PMD register. The data
serialization ensures that all prior PMD reads and writes as well as all prior PMC writes
have completed.
Table 7-5.
PSR.sp
2:158
Generic Performance Counter Configuration Register Fields
(PMC[4]..PMC[p]) (Continued)
Bits
6 Privileged monitor – When 0, the performance monitor is configured as a user monitor,
and enabled by PSR.up. When PMC.pm is 1, the performance monitor is configured as
a privileged monitor, enabled by PSR.pp, and the corresponding PMD can only be read
by privileged software.
7 ignored
15:8 Event select – selects the performance event to be monitored. Actual event encodings
are implementation dependent. Some processor models may not implement all event
select (es) bits. At least one bit of es must be implemented on all processors.
Unimplemented es bits are ignored.
63:16 Implementation-specific bits – Reads from implemented bits return
implementation-dependent values. For portability, software should write what was read;
i.e., software may not use these bits as storage. Hardware will ignore writes to
unimplemented bits.
summarizes the effects of PSR.sp, PMC[i].pm, and PSR.cpl on reading PMD
Reading Performance Monitor Data Registers
PMC[i].pm
0
0
1
1
0
Description
PSR.cpl
0
1
0
1
0
Volume 2, Part 1: Debugging and Performance Monitoring
PMD Reads Return
0 PMD value
0 PMD value
0 PMD value
0 PMD value
>0 PMD value