Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 405

A counter overflow interrupt occurs when the counter wraps; i.e., a carry out from bit
W-1 is detected. Counter overflow interrupts are edge-triggered; that is, the event of a
counter incrementing and causing carry out from bit W-1 thus setting the overflow bit
and the freeze bit, generates one PMU interrupt. Provided that software does not clear
the freeze bit, while either or both of PSR.up and pp are 1, without also clearing the
overflow bit (before or concurrent with the write to the freeze bit), no further interrupts
are generated based on the fact that the carry out had been earlier detected.
Figure 7-4
and Table 7-4
Figure 7-4.
PMD[4]..PMD[p]
Table 7-3.
Field
ig
count
Some implementations do not treat the upper, unimplemented bits of PMDs as ignored
bits on reads, but rather return a copy of bit W-1 in these bit positions so that count
values appear as if they were sign extended. Subsequent implementations will return 0
for these bits on reads.
Figure 7-5.
PMC[4]..PMC[p]
Table 7-4.
Field
plm
ev
oi
Volume 2, Part 1: Debugging and Performance Monitoring
and Figure 7-5 show the fields in PMD and PMC respectively, while
describe the fields in PMD and PMC respectively.
Generic Performance Counter Data Registers (PMD[4]..PMD[p])
63
ig
64-W
Generic Performance Counter Data Register Fields
Bits
63:W Writes are ignored. Reads return 0.
W-1:0 Event Count. The counter is defined to overflow when the count field wraps (carry out
from bit W-1).
Generic Performance Counter Configuration Register
(PMC[4]..PMC[p])
63
implementation specific
48
Generic Performance Counter Configuration Register Fields
(PMC[4]..PMC[p])
Bits
3:0 Privilege Level Mask – controls performance monitor operation for a specific privilege
level. Each bit corresponds to one of the 4 privilege levels, with bit 0 corresponding to
privilege level 0, bit 1 with privilege level 1, etc. A bit value of 1 indicates that the monitor
is enabled at that privilege level. Writing zeros to all plm bits effectively disables the
monitor. In this state, the corresponding PMD register(s) do not preserve values, and
the processor may choose to power down the monitor.
4 External visibility – When 1, an external notification (such as a pin or transaction) may
be provided, dependent upon implementation, whenever the monitor overflows.
Overflow occurs when a carry out from bit W-1 is detected.
5 Overflow interrupt – If 1, when the monitor overflows, a Performance Monitor Interrupt is
raised and the performance monitor freeze bit (PMC[0].fr) is set. If 0, no interrupt is
raised and the performance monitor freeze bit (PMC[0].fr) remains unchanged.
Overflow occurs when a carry out from bit W-1 is detected. See
Overflow Status Registers (PMC[0]..PMC[3])"
vectors.
W W-1
count
W
Description
16 15 8 7
es
8
Description
"Performance Monitor
for details on configuring interrupt
Table 7-3
0
6 5 4 3 0
ig pm oi ev plm
1 1 1 1 4
2:157