Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 860

10.5.8 Inter-processor Interrupts Layout and Example
A processor generates an inter-processor interrupt (IPI) by storing a 64-bit interrupt
command to an 8-byte aligned address in the Interrupt delivery region of the Processor
Interrupt block. The address being stored to determines what target processor receives
the IPI. The example below is an example of sending an interrupt to a specific
processor based on the destination ID passed in. The destination ID consists of the
Local interrupt ID and the Extended interrupt ID.
Writing to improperly aligned addresses in the delivery region or failure to store less
than 64 bits can result in an invalid operation fault. The access must be uncacheable in
order to generate an IPI.
//
// send_ipi_physical (dest_id, vector)
//
// inputs:
//
//
//
//
.global ipi_block
IPI_DEST_EID=0x4
ENTRY(send_ipi_physical)
END(send_ipi_physical)
10.5.9 INTA Example
External interrupt controllers, that are compatible with the Intel 8259A interrupt
controller can not issue interrupt messages, so the vector number is not available at
the time of the interrupt request. When an interrupt is accepted the software must
check to see if it came from an external controller by the vector number (via IVR) to
see if it is the ExtINT vector.
2:612
processor destination ID vector to send
(Local ID (8 bits << 8)| EID ( 8 bits))
alloc r19=ar.pfs,2,0,0,0
movl r17=ipi_block;;
ld8 r17=[r17]
shl r21=r32,IPI_DEST_EID;;
add r20=r21,r17;;
st8.rel [r20]=r33
br.ret.sptk b0;;
// pointer to processor I/O block
// get pointer to processor block
// point to proper processor
// send the IPI
Volume 2, Part 2: External Interrupt Architecture