Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 735

Table 11-121. State Requirements for PSR for PAL Virtualization Services
PSR Bit
be
up
ac
mfl
mfh
ic
i
pk
dt
dfl
dfh
sp
pp
di
si
db
lp
tb
rt
cpl
is
mc
it
id
da
dd
ss
ri
ed
bn
ia
vm
a. PAL services can be called with PSR.be bit equal to 0 or 1. The behavior is undefined if PSR.be setting does
not match the be parameter during PAL_VP_INIT_ENV. See
Environment (268)" on page 2:478
b. Most PAL services are invoked with PSR.ic equal to 0.
Volume 2, Part 1: Processor Abstraction Layer
big-endian memory access enable
user performance monitor enable
alignment check
floating-point registers f2-f31 written
floating-point registers f32-f127 written
interruption state collection enable
interrupt enable
protection key validation enable
data address translation enable
disabled FP register f2 to f31
disabled FP register f32 to f127
secure performance monitors
privileged performance monitor enable
disable ISA transition
secure interval timer
debug breakpoint fault enable
lower-privilege transfer trap enable
taken branch trap enable
register stack translation enable
current privilege level
instruction set
machine check abort mask
instruction address translation enable
instruction debug fault disable
data access and dirty-bit fault disable
data debug fault disable
single step trap enable
restart instruction
exception deferral
register bank
instruction access-bit fault disable
processor virtualization
for details.
Description
"PAL_VP_INIT_ENV – PAL Initialize Virtual
Value
a
-
-
-
-
-
b
0
c
-
0
-
1
-
-
-
-
-
-
0
-
0
1
0
0
-
1
-
-
-
0
-
-
d
-
e
0
-
0
2:487