Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 556

• DBR/IBRs: The contents of all breakpoint registers are unchanged from the time of
the INIT.
• PMCs/PMDs: The contents of the PMC registers are unchanged from the time of the
INIT. The contents of the PMD registers are not modified by PAL code, but may be
modified if events it is monitoring are encountered.
• Cache: The contents of the caches are unchanged from the time of the INIT.
• TLB: The TCs may be initialized and the TRs are unchanged from the time of the
INIT.
• Interruption Resources:
• IRR: PALE_INIT may not change the IRR, but interrupts may have arrived
asynchronously, changing the contents of the IRRs.
• The contents of IIP, IPSR and IFS at the time of INIT are saved to the min-state
save area and are available for use.
11.4.2.1 Processor State Parameter (GR18)
Figure 11-5.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
gr b0 b1 fp pr br ar rr tr dr pc cr ex cm rs in dy pm pi mi tl hd us ci co sy mn me ra rz rsvd
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
uc rc bc tc cc
The term "valid" in
the time of interruption or that the values have been preserved in the min-state save
area.
Table 11-12. Processor State Parameter Fields
Field Bits
rsvd 1:0
rz 2
ra 3
me 4
mn 5
sy 6
co 7
ci 8
2:308
Processor State Parameter
reserved
Table 11-7 indicates that the registers are either unchanged from
INIT
value
Reserved
a
x The attempted processor rendezvous was successful if set to 1.
a
x A processor rendezvous was attempted if set to 1.
0 Distinct multiple errors have occurred, not multiple occurrences of a single error.
Software recovery may be possible if error information has not been lost.
a
x Min-state save area has been registered with PAL if set to 1.
0 Storage integrity synchronized. A value of 1 indicates that all loads and stores prior to
the instruction on which the machine check occurred completed successfully, and
that no loads or stores beyond that point occurred. See
1 Continuable. A value of 1 indicates that all in-flight operations from the processor
where the machine check occurred were either completed successfully (such as a
load), were tagged with an error indication (such as a poisoned store), or were
suppressed and will be re-issued if the current instruction stream is restarted. This bit
can only be set if the architectural state saved on a machine check is all valid. If this
bit is set, then us must be cleared to 0, and ci must be set to 1. See
1 Machine check is isolated. A value of 1 indicates that the error has been isolated by
the system, it may or may not be recoverable. If 0, the hardware was unable to isolate
the error within the CPU and memory hierarchy. The error may have propagated off
the system (to persistent storage or the network). If ci = 0 then us will be set to 1, and
co and sy are cleared to 0. See
8
se dsize
Description
Table
Table 11-8.
Volume 2, Part 1: Processor Abstraction Layer
7 6 5 4 3 2 1 0
36 35 34 33 32
11-8.
Table 11-8.