Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 487

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Itanium Architecture-based Operating
System Interaction Model with IA-32
Applications
This section describes the IA-32 system execution model from the perspective of an
Itanium architecture-based operating system interfacing with IA-32 code, while
operating in the Itanium System Environment. The main features covered are:
• IA-32 system and control register behavior
• IA-32 virtual memory support
• IA-32 fault and trap handling
• IA-32 instruction behavior
10.1 Instruction Set Transitions
Instruction set transitions are defined in
page 1:110. Operating systems can disable instruction set transitions (jmpe and br.ia)
by setting PSR.di to one. If PSR.di is one, execution of jmpe or br.ia to IA-32 target
results in a Disabled Instruction Set Transition Fault, and the operation is nullified.
The processor also transitions into an Itanium architecture-based operating system
when IA-32 privileged system resources are accessed, on an interruption, or when the
following conditions are detected:
• Instruction Interception
• System Flag Interception
and IF-bits)
• Gate Interception
through a task switch (TSS segment or Task Gate).
All software interrupts, external interrupts, faults, traps and machine checks transition
the processor to the Itanium instruction set, regardless of the state of PSR.di. IA-32
defined exceptions and software interrupts are delivered to Itanium architecture-based
interruption handlers.
10.2 System Register Model
Registers are assigned the following conventions during transitions between IA-32 and
Itanium instruction sets.
• IA-32 State: The register contains an IA-32 register during IA-32 instruction set
execution. Expected IA-32 values should be loaded before switching to the IA-32
instruction set. After completion of IA-32 instructions, these registers contain the
results of the execution of IA-32 instructions. These registers may contain any
value during Itanium instruction execution according to Itanium software
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Volume 2, Part 1: Itanium Architecture-based Operating System Interaction Model with IA-32 Applications
Section 6.2.1, "Instruction Set Modes" on
IA-32 system level privileged instructions are executed
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Various EFLAG system flags are modified, (e.g. AC, TF
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Control transfers are made through call gate, or transfers
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