Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 525

Table 10-9.
IA-32
Vector
IA_32_Intercept(Inst)
IA_32_Intercept(Gate)
IA_32_Intercept(SystemFlag)
IA_32_Intercept(Lock)
a. The IA-32 Error Code is defined as a Selector Index, and TI, IDT and EXT bits are set based on the
exception. See Intel
definition.
10.9.2 IA-32 Numeric Exception Model
IA-32 numeric instructions follow the IA-32 delayed floating-point exception model.
Specifically IA-32 numeric exceptions are held pending until the next IA-32 numeric or
MMX technology instruction as defined in the Intel
Software Developer's Manual. Numeric faults generated on SSE instructions are
reported precisely on the faulting SSE instruction. SSE instructions do NOT trigger the
report of pending IA-32 numeric exceptions.
For voluntary transitions out of the IA-32 instruction, an implicit FWAIT operation is
performed by the jmpe instruction to ensure all pending numeric exceptions are
reported. For involuntary transitions out of the IA-32 instruction set (external
interruptions, TLB faults, exceptions, etc.) the processor does not perform a FWAIT
operation. However, every IA-32 numeric instruction that generates a pending numeric
exception loads the application registers FSR, FIR, and FDR with the IA-32
floating-point state on the instruction that generating the exception. This state contains
information defined by the IA-32 FSTENV and FLDENV instructions. During a process
context switch, the operating system must save and restore FSR, FIR, and FDR
(effectively performing an FSTENV and FLDENV) to ensure numeric exceptions are
correctly reported across a process switch.
10.10 Processor Bus Considerations for IA-32
Application Support
The section briefly discusses bus and platform considerations when supporting IA-32
applications in the Itanium System Environment.
Itanium architecture-based code does not assert the SPLCK and LOCK pins. The LOCK
pin is used by IA-32 code to signal an external atomic bus transaction for which
atomicity cannot be enforced within the processor's caches, whereas, SPLCK indicates if
an unaligned external bus lock requires a split lock operation and hence several bus
®
Volume 2, Part 1: Itanium Architecture-based Operating System Interaction Model with IA-32 Applications
IA-32 Interruption Summary (Continued)
®
Itanium Architecture-based
Interruption Handler
®
64 and IA-32 Architectures Software Developer's Manual for the complete
ISR ISR
Vector Code
0 InterceptCode
1 TrapCode
2 TrapCode
4 0
3,5-25 --
5
®
64 and IA-32 Architectures
Description
Intercept for unimplemented, illegal
or privileged IA-32 opcodes.
Intercept for control transfers
through a Call Gate, Task gate or
Task Segment.
Intercept for modification of system
flag values.
IA-32 semaphore operation
requires an external bus lock when
DCR.lc is 1.
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