Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 890

movl r2 = 0x0
;;
mov
//Setup ITIR (Interruption TLB Insertion Register)
movl r3 = ( ( 24 << 2 ) | ( 0 << 8 ) )
;;
mov
//Now setup the general register to use with itr (insert translation
//register)
movl r10 =( (1 << 52 ) | (0x0 << 12 ) | (3 << 9 ) | (0 << 7) |\
;;
itr.d dtr[r11] = r10
;;
//It is now time to set the appropriate bits in the PSR (processor
//status register)
movl r3 = ( (1 << 44) | (1 << 36) |(1 << 38) |(1 << 27) |(1 << 17) | \
;;
mov cr.ipsr = r3
//Initialize DCR to defer all speculation faults
movl r2 = 0x7f00
;;
mov cr.dcr = r2
// Initialize the global pointer (gp = r1)
movl gp = __GLOB_DATA_PTR
// Clear out ifs
mov cr.ifs=r0
// Need to do a "rfi" in order to synchronize above instructions and set
// "it" and "ed" bits in the PSR.
movl r3 = main
;;
mov cr.iip = r3
;;
rfi
;;
// Setup kernel stack
.data
.globalkstack
.align 16
kstack:
.skip(64*1024)
2:642
cr.ifa = r2
cr.itir = r3
(1 << 6) | ( 1 << 5 ) | (1 << 0))
(1 << 15) | (1 << 14) | (1 <<
// use vpn 0
// 16 MB
// Insert translation register
13))
// Setup for main, C code
// Setup iip to hit main
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Volume 2, Part 2: Code Examples