Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 578
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Table 11-19. Virtualization Acceleration Control (vac) Fields (Continued)
Field
a_to_int_cr
a_from_psr
a_from_cpuid
a_cover
a_bsw
a_all_probes
a_select_probes
a_tf
a_ic_um
Reserved
Figure 11-14. Virtualization Disable Control (vdc)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Table 11-20. Virtualization Disable Control (vdc) Fields
Field
d_vmsw
d_extint
d_ibr_dbr
d_pmc
2:330
Bit
2
Enable the interruption control register (CR16-27) write optimization. See
Section 11.7.4.2.3, "Interruption Control Register Write Optimization" on
page 2:341
for details.
3
Enable the processor status register read optimization. See
Section 11.7.4.2.4, "MOV-from-PSR Optimization" on page 2:341
4
Enable the CPUID read optimization. See
"MOV-from-CPUID Optimization" on page 2:342
5
Enable the cover instruction optimization. See
Optimization" on page 2:343
6
Enable the bsw instruction optimization. See
Optimization" on page 2:343
7
Enable virtualization of probe instructions. See
Instruction Virtualization" on page 2:344
8
9
Enable the test feature optimization. See
Optimization" on page 2:345
10
Enable the interruption collection and user mask optimization. See
Section 11.7.4.2.10, "Interruption Collection and User Mask Optimization" on
page 2:345
for details.
63:11
Reserved
Reserved
Reserved
Bits
0
Disable vmsw instruction – If 1, disables vmsw instruction on the logical pro-
cessor. Execution of the vmsw instruction, independent of the state of
PSR.vm, will cause a virtualization intercept.
1
Disable external interrupt control register virtualization – If 1, accesses
(reads/writes) of the external interrupt control registers (CR65-71) are not vir-
tualized. Code running with PSR.vm==1 can read and write the external inter-
rupt control registers of the logical processor directly and without handling off
to the VMM. See
Section 11.7.4.3.2, "Disable External Interrupt Control Reg-
ister Virtualization" on page 2:347
2
Disable breakpoint register virtualization – If 1, accesses (reads/writes) of the
data and instruction breakpoint registers (IBR/DBR) are not virtualized. Code
running with PSR.vm==1 can read and write the data/instruction breakpoint
registers of the logical processor directly and without handling off to the VMM.
If 0, accesses of the breakpoint registers with PSR.vm==1 result in virtualiza-
tion intercepts.
3
Disable PMC virtualization – If 1, accesses (reads/writes) of the performance
monitor configuration registers (PMCs) are not virtualized. Code running with
PSR.vm==1 can read and write the performance monitor configuration regis-
ters of the logical processor directly and without handling off to the VMM.
If 0, accesses of the performance counter configuration registers with
PSR.vm==1 result in virtualization intercepts.
Description
Section 11.7.4.2.5,
for details.
Section 11.7.4.2.6, "Cover
for details.
Section 11.7.4.2.7, "Bank Switch
for details.
Section 11.7.4.2.8, "Probe
for details.
Section 11.7.4.2.9, "Test Feature
for details.
8
7
6
Disable Controls
Description
for details.
Volume 2, Part 1: Processor Abstraction Layer
for details.
5
4
3
2
1
0
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