Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 325

Table 4-12.
Bit{63}
0
1
a. Coherency here refers to multiprocessor coherence on normal, side-effect free memory.
See "Speculation Attributes" on page 2:79
limited speculation. Bit{63} is discarded when forming the physical address, effectively
creating a write-back name space and an uncached name space as shown in
Figure 4-21.
Figure 4-21.
Software must use the correct name space when using physical addressing; otherwise,
I/O devices with side-effects may be accessed speculatively. Physical addressing
accesses are ordered only if ordered loads or ordered stores are used. Otherwise,
physical addressing memory references are unordered.
4.4.3 Cacheability and Coherency Attribute
A page can be either cacheable or uncacheable. If a page is marked cacheable, the
processor is permitted to allocate a local copy of the corresponding physical memory in
all levels of the processor memory/cache hierarchy. Allocation may be modified by the
cache control hints of memory reference instructions.
A page which is cached is coherent with memory; i.e., the processor and memory
system ensure that there is a consistent view of memory from each processor.
Processors support multiprocessor cache coherence based on physical addresses
between all processors in the coherence domain (tightly coupled multiprocessors).
Coherency is supported in the presence of virtual aliases, although software is
recommended to use aliases which are an integer multiple of 1 MB apart to avoid any
possible performance degradation.
Processors are not required to maintain coherency between processor local instruction
and data caches for Itanium architecture-based code; i.e., locally initiated Itanium
stores may not be observed by the local instruction cache. Processors are required to
Volume 2, Part 1: Addressing and Protection
Physical Addressing Memory Attribute Encodings
Mnemonic Cacheability
WBL Cacheable
UC Uncached
Addressing Memory Attributes
64
2 Base Register
64
2
Uncached
Non-speculative
Name Space
63
2
Cached Write-back
Limited Speculation
Name Space
0
Write Policy
Write Back Non-sequential &
limited speculation
Non-coalescing Sequential &
non-speculative
for a description of physical addressing
UC
WBL
Coherent
Speculation
respect to
WBL, WB
UC, UCE
63
2 Physical
Address Space
63
2
a
with
2:77