Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 558

Table 11-12. Processor State Parameter Fields (Continued)
Field Bits
rc 62
uc 63
a. The values of the fields marked with x are set by the PAL INIT handler based on the INIT handling.
11.4.2.2 Definition of SALE_ENTRY State Parameter
Figure 11-6.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
• function
Table 11-13. function Field Values
RESET
MACHINE CHECK
INIT
RECOVERY CHECK
All other values of function are reserved.
11.5 Platform Management Interrupt (PMI)
11.5.1 PMI Overview
PMI is an asynchronous interrupt that encapsulates a collection of platform-specific
interrupts. Platform Management Interrupts occur during instruction processing,
causing the flow of control to be passed to the PAL PMI handler. In the process, state is
saved in the interruption registers (IIP, IPSR) by the processor hardware and the
processor starts executing instructions at the PALE_PMI entrypoint. The PAL code will
save some additional state in the bank 0 registers. The PAL will either handle the PMI if
it is PAL related PMI or transition to the SAL PMI code if it is a SAL related PMI. Upon
completion of processing, the SAL PMI code returns to PAL PMI code to restore the
interrupted processor state and to resume execution at the interrupted instruction.
As shown in
PMI handler which handles all processor-specific processing, and the SAL PMI handler
which handles all platform-related processing. The location of the PALE_PMI and
SALE_PMI handlers are programmable. The location of the PALE_PMI handler can be
programmed by the PAL_COPY_PAL procedure described on
handler can be programmed by the PAL_PMI_ENTRYPOINT procedure described on
page 2:443. If a PMI is taken very early in the boot sequence before PAL has a chance
2:310
INIT
value
0 Register file check. A value of 1 indicates that a register file related machine check
occurred. See the PAL_MC_ERROR_INFO procedure call for more information.
0 Uarch check. A value of 1 indicates that a micro-architectural related machine check
occurred. See the PAL_MC_ERROR_INFO procedure call for more information.
SALE_ENTRY State Parameter
reserved
An 8-bit field indicating the reason for branching to SALE_ENTRY.
–
Function Value
0
1
2
3
Figure 11-7, PMI code consists of two major components, namely the PAL
Description
reserved
Description
System reset or power-on
Machine check event
Initialization event
Check for recovery condition in SAL
Volume 2, Part 1: Processor Abstraction Layer
8 7 6 5 4 3 2
function
page 2:389. The SALE_PMI
1 0