Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 818

5.2.2.2.3
The Itanium architecture supports efficient global TLB shootdowns via the ptc.g and
ptc.ga instructions. These instructions obviate the need for performing inter-processor
interrupts to maintain TLB coherence in a multiprocessor system. A TLB coherence
domain is defined as a group of processors in a multiprocessor system which maintain
TLB coherence via hardware.
For the remainder of this section, ptc.g refers to both the ptc.g and ptc.ga
instructions, except where otherwise noted.
The number of ptc.g operations that can be in progress at any time is implementation
dependent, and can be determined from the max_purges return parameter of
PAL_VM_SUMMARY. Attempting to execute more than the maximum allowed number of
simultaneous ptc.g purges will have undefined effects, including possibly raising a
Machine Check Abort on one or more processors. Software should implement some
semaphoring mechanism to ensure that not more than the maximum ptc.g purges
allowed are in flight at any one time.
A ptc.g instruction is a release operation; all memory references that precede a ptc.g
in program order are made visible to all other processors before the ptc.g is made
visible. To guarantee visibility of the ptc.g prior to a particular point in program
execution, software must use another release operation or a memory fence.
To purge a translation from all TLBs in the coherence domain, software performs the
following steps:
1. Acquire the semaphore.
2. Place the base virtual address of the translation to be purged into a general
register.
3. Place the address range in bytes of the purge into bits {7:2} of a second general
register.
4. Using these two GRs, execute the ptc.g instruction. Note that the ptc.g
instruction must be followed by a stop.
5. Release the semaphore.
Global purges can be batched together by performing multiple ptc.g instructions prior
to releasing the lock.
A data or instruction serialization operation must be performed after the sequence
shown above before the translations are guaranteed to be no longer visible to the local
data or instruction stream, respectively. To guarantee the translations are no longer
visible on remote processors, a release operation or memory fence instruction is
required after the ptc.g instruction.
The ptc.g instruction does not modify the page tables nor any other memory location.
It affects both the local and all remote TC entries in the TLB coherence domain. It does
not remove translations from either local or remote TR entries. If a ptc.g overlaps a
translation contained in a TR on the local processor, the local processor will raise a
Machine Check Abort; if the ptc.g overlaps a translation contained in a TR on any
remote processor in the coherence domain, no Machine Check Abort is raised.
2:570
ptc.g, ptc.ga
Volume 2, Part 2: Memory Management