Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 450

Unsupported Data Reference vector (0x5b00)
Name
Cause An attempt was made to:
• Execute a fetchadd, cmpxchg, xchg, or unsupported ld16, st16 or 10-byte
memory reference (ldfe or stfe) instruction to a page that is neither cacheable
with write-back write policy nor a NaTPage.
• Execute a fetchadd instruction to a page that is an uncacheable exported (UCE)
page and the processor model does not support exporting of fetchadd instructions.
See "Effects of Memory Attributes on Memory Reference Instructions" on page 2:86
details. IA-32 instructions can not raise this fault, IA-32 locked faults are delivered on
the IA_32_Intercept(Lock) vector.
If the data reference specified is both unaligned to the natural datum size and
unsupported, then an Unaligned Data Reference fault is taken.
IA-32 data memory references that require an external atomic lock when DCR.lc is 1,
raise an IA_32_Intercept(Lock) fault; see
Descriptions."
Interruptions on this vector:
Unsupported Data Reference fault
Parameters IIP, IPSR, IIPA, IFS – are defined; refer to
IFA – The address of the data being referenced.
IIB0, IIB1 – If implemented, the IIB registers contain the instruction bundle pointed to
by IIP. Please refer to
(IIB0-1 – CR26, 27)" on page 2:42
ISR – The value for the ISR bits depend on the type of access performed and are
specified below.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
For ldfe and stfe instructions, the processor may optionally set both ISR.r and ISR.w
to 1, although this is not recommended.
2:202
Section 3.3.5.10, "Interruption Instruction Bundle Registers
0 0
0
Chapter 9, "IA-32 Interruption Vector
page 2:165 for a detailed description.
for details on the IIB registers.
ed
Volume 2, Part 1: Interruption Vector Descriptions
8 7 6 5 4 3 2
0
ei 0 ni 0 0 0 0 r w 0
for
1 0