Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 453

Lower-Privilege Transfer Trap vector (0x5e00)
Name
Cause Two trapping conditions transfer control to this vector:
• An attempt is made to transfer control to an unimplemented address, resulting in
either an Unimplemented Instruction Address trap or an Unimplemented Instruction
Address fault.
• The PSR.lp bit is 1, and a branch lowers the privilege level.
IA-32 instructions can not raise this trap.
Interruptions on this vector:
Unimplemented Instruction Address fault
Unimplemented Instruction Address trap
Lower-Privilege Transfer trap
Parameters IIP, IPSR, IIPA, IFS – are defined; refer to
Note: Please see
for a further clarification of the IIP value for an unimplemented instruction
address trap.
IIB0, IIB1 – If implemented, for Lower-Privilege Transfer traps, the IIB registers
contain the instruction bundle pointed to by IIPA. The IIB registers are undefined for
Unimplemented Instruction Address faults and traps. Please refer to
"Interruption Instruction Bundle Registers (IIB0-1 – CR26, 27)" on page 2:42
details on the IIB registers.
ISR – For Unimplemented Instruction Address trap and Lower-Privilege Transfer trap,
the ISR.ei bits are set to indicate which instruction caused the exception, and the
ISR.code contains a bit vector (see
occurred in the just-executed instruction.
For Unimplemented Instruction Address fault ISR.fp_trap_code is set to 0.
The defined ISR bits are specified below.
If this vector was entered for an Unimplemented Instruction Address fault:
IFA – Faulting unimplemented instruction address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
If this vector was entered for an Unimplemented Instruction Address trap:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
If this vector was entered for a Lower-Privilege Transfer trap:
Volume 2, Part 1: Interruption Vector Descriptions
See "Unimplemented Address Bits" on page 2:73.
"Interruption Instruction Bundle Pointer (IIP – CR19)" on page 2:37
0 0
0
0 0
0
page 2:165 for a detailed description.
Table 8-3 on page 2:170) for all traps which
0 0
0
0 fp trap code
0
Section 3.3.5.10,
for
8 7 6 5 4 3 2
0 0 1 0 0 0 0
ri 0 ni ir 0 0 0 0 0 1
8 7 6 5 4 3 2
0 0 1 ss tb lp fp
ei 0 ni ir 0 0 0 0 0 0
1 0
1 0
2:205