Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 800

In principal, preserved GRs and FRs need not be spilled/filled when entering the kernel.
Whatever function is called from the low-level interruption handler or the system call
entry point will itself observe the calling conventions and preserve the registers. The
only occasion when preserved registers need to be spilled/filled is on a process or
thread context switch. However, many operating systems provide get_context()
functions that provide user context upon demand. Although such functions are called
infrequently, many operating systems prefer to pay the penalty of spilling preserved
registers at system call and at interruption entry points to avoid the complexity of
piecing together user state from various potentially unknown kernel stack locations on
demand. Fortunately, the amount of preserved Itanium general register state is
relatively small, and the Itanium architecture provides additional mechanisms for lazy
floating-point state management. See
Table 4-2.
Register Type
Scratch GRs
Preserved GRs
Stacked GRs
Scratch FRs
Preserved FRs
a. For details on lightweight interruption handlers refer to
page 2:543.
b. For details on heavyweight interruption handlers refer to
page 2:544.
c. Refer to
Stacked GRs are managed by the register stack engine (RSE). On process/thread
context switches the operating system is required to completely flush the register stack
to its backing store in memory (using the flushrs instruction). In cases where the
operating system knows that it will return to the user process along the same path, e.g.
in system calls and exception handling code, the Itanium architecture allows operating
systems to switch the register stack backing store without having to flush all stacked
registers to memory. This allows such kernel entry points to switch from the user's to
the kernel's backing store without causing any memory traffic, as described in the next
section.
4.2.1 Preservation of Stacked Registers in the OS
A switch from a thread of execution into the operating system kernel, whether on
behalf of an involuntary interruption or a voluntary system call, requires preservation of
the stacked registers. Instead of flushing all dirty stacked register's to memory, the RSE
can be used to automatically preserve the stacked registers of the interrupted context.
2:552
Register State Preservation at Different Points in the OS
Number of System Call
Registers (Voluntary)
23 no spill/fill
4 no spill/fill
96 Backing Store
106 no spill/fill
20 no spill/fill
Section 6.11.3, "Synchronous Backing Store Switch"
Section 4.2.2 for details.
Lightweight
Interrup-
a
tions
(Involuntary)
Untouched
required (use banked
registers)
Untouched
required (use banked
registers)
Untouched
Switch
Untouched
required
Untouched
required
Section 3.4.1, "Lightweight Interruptions" on
Section 3.4.2, "Heavyweight Interruptions" on
for details.
Heavyweight
Process/Thread
Interrup-
Context Switch
b
tions
(Voluntary)
(Involuntary)
spill/fill no spill/fill required
required (done at interruption)
no spill/fill spill/fill
required required
Backing Store Synchronous
Switch Backing Store Switch
using flushrs
spill/fill no spill/fill required
required (done at interruption)
no spill/fill spill/fill
required required
Volume 2, Part 2: Context Management
c