Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 546

• GR16 through GR20 (bank 0) contain parameters which PALE_CHECK passes to
SALE_ENTRY for diagnostic and recovery purposes:
• FRs: The contents of all floating-point registers are unchanged from the time of the
MCA.
• Predicates: All predicate registers have been saved in the min-state save area and
are available for use.
• BRs: The contents of all branch registers are unchanged from the time of the MCA,
except the following.
• BR0 and BR1 have been saved to the min-state save area and are available for
use. Either register may have been changed from the time of entry into
PALE_CHECK.
• ARs: The contents of all application registers are unchanged from the time of the
MCA, except the RSE control register (RSC), the RSE backing store pointer (BSP),
and the ITC and RUC counters. The RSC register is unchanged, except that the
RSC.mode field will be set to 0 (enforced lazy mode) and the RSC register at the
time of the MCA has been saved in the min-state save area. A cover instruction is
executed in the PALE_CHECK handler which allocates a new stack frame of zero
size. BSP will be modified to point to a new location, since all the registers from the
current frame at the time of interruption were added to the RSE dirty partition by
the allocation of a new stack frame. The ITC register will not be directly modified by
PAL, but will continue to count during the execution of the MCA handler. The RUC
register will not be directly modified by PAL, but will continue to count during the
execution of the MCA handler while the processor is active.
• CFM: The CFM register points to a zero-size current frame and all the rotating
register bases are set to zero. The CFM register at the time of the MCA has been
saved to the min-state save area in either the IFS or XFS slot depending on the
implementation.
• RSE: Is in enforced lazy mode, and stacked registers are unchanged from the time
of the MCA.
• PSR: PSR.mc is 1; PSR.mfl, PSR.mfh, and PSR.pk are unchanged; all other bits are
0. The PSR at the time of the MCA is saved in the min-state save area.
• CRs: The contents of all control registers are unchanged from the time of the MCA
with the exception of interruption resources, which are described below.
• RRs: The contents of all region registers are unchanged from the time of the MCA.
• PKRs: The contents of all protection key registers are unchanged from the time of
the MCA.
• DBR/IBRs: The contents of all breakpoint registers are unchanged from the time of
the MCA.
• PMCs/PMDs: The contents of the PMC registers are unchanged from the time of the
MCA. The contents of the PMD registers are not modified by PAL code, but may be
modified if events it is monitoring are encountered.
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• GR16 contains the address to the first available location in the min-state
save area for use by SAL. The address is 8-byte aligned.
• GR17 contains the value of the min-state save area address stored in XR0.
• GR18 contains the Processor State Parameter, as defined in
• GR19 contains the PALE_CHECK return address for rendezvous, or 0 if no
return is expected. (See Section 11.3.2.2, "Multiprocessor Rendezvous
Requirements for Handling Machine Checks")
• GR20 contains the SALE_ENTRY State Parameter as defined in
Figure
Volume 2, Part 1: Processor Abstraction Layer
11-11.
Figure 11-4.