Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 316

operating systems must ensure that the VHPT is aligned on the natural boundary of the
structure; otherwise, processor operation is undefined. For example, a 64K-byte table
must be aligned on a 64K-byte boundary.
VHPT walker references to the VHPT are performed at privilege level 0, regardless of
the state of PSR.cpl. VHPT byte ordering is determined by the state of DCR.be. When
DCR.be=1, VHPT walker references are performed using big-endian memory formats;
otherwise, VHPT walker references are little-endian. A long-format VHPT reference is
matched against the data break-point registers as a 32-byte reference.
The VHPT is accessed by the processor only if the VHPT is virtually mapped into
cacheable memory areas. The walker may access the VHPT speculatively, i.e.,
references may be performed that are not required by an in-order execution of the
program. Any VHPT or TLB faults encountered during a VHPT walker's search are not
reported until the faulting translation is required by an in-order execution of the
program. If the VHPT is mapped into non-cacheable memory areas the VHPT is not
referenced, and all TLB misses result in an Instruction/Data TLB Miss fault.
The VHPT walker will abort the search and deliver an Instruction/Data TLB Miss fault if
an attempt is made to install translations that have reserved bits or encodings, or if the
translation mapping the VHPT would have taken one of the following faults: Data Page
Not Present, Data NaT Page Consumption, Data Key Miss, Data Key Permission, Data
Access Bit, or Data Debug. The VHPT walker may abort a search and deliver an
Instruction/Data TLB Miss fault at any time for implementation-specific reasons.
The processor's VHPT walker is required to read and insert VHPT entries from memory
atomically (an 8-byte atomic read-and-insert for short format, and a 32-byte atomic
read-and-insert for long format). Some implementation strategies for achieving this
atomicity are as follows:
• If the walker performs its VHPT read with multiple cache accesses which are not
done as an atomic unit, and if an update to part of the entry that is being installed
is made in-between these multiple reads, the walker must abort the insert and
deliver an Instruction/Data TLB Miss.
• If the walker performs its VHPT read and the insertion of the entry into the TLB as
separate actions, and not as an atomic unit, and if an update to part of the entry
that is being installed is made in-between the read and the insert, the walker must
either abort the insert and deliver an Instruction/Data TLB Miss, or ignore the
update and install the complete old entry.
• If the purge address range of a TLB purge operation (ptc.l, ptc.e, local or remote
ptc.g or ptc.ga, ptr.i, or ptr.d) overlaps the virtual address the walker is
attempting to insert, then the walker must either abort the insert and deliver an
Instruction/Data TLB Miss, or delay the purge operation until after the walker either
completes the insertion or aborts the walk.
The RSE can only raise a VHPT fault on a mandatory RSE spill/fill operation as defined
for successful execution of an alloc, loadrs, flushrs, br.ret or rfi instruction.
Eager RSE operations may generate speculative VHPT walks provided encountered
faults are not reported.
Data TLB Miss faults encountered during a VHPT walk are permitted and, when
PSR.ic=1, are converted into a VHPT Translation fault as defined in the next section.
2:68 Volume 2, Part 1: Addressing and Protection