Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 413

Interruption Vector Descriptions
Chapter 5
Itanium architecture. This chapter describes the IVA-based interruption handlers.
"Interruption Vector Descriptions"
vectors and
vectors. PAL-based interruptions are described in
Layer." Note that unless otherwise noted, references to "interruption" in this chapter
refer to IVA-based interruptions. See
8.1 Interruption Vector Descriptions
The section lists all the Itanium interruption vectors. It describes the interruption
vectors and the parameters that are defined when the vector is entered.
If an interruption is independent of the executing instruction set (including IA-32), such
as an external interrupt or TLB fault, common Itanium interruption vectors are used.
For exceptions and intercept conditions that are specific to the IA-32 instruction set
three IA-32 specific vectors are used; IA_32_Exception, IA_32_Interrupt, and
IA_32_Intercept.
Table 8-1
undefined for each interruption vector. The individual vector descriptions below list
interruption-specific resources for each vector.
See "IVA-based Interruption Handling" on page 2:101
handles an interruption. See
definition of bit fields within the interruption resources.
8.2 ISR Settings
For each of the interruption vectors, a figure depicts the ISR setting. These figures
show the value that hardware writes into the ISR for the corresponding interruption.
Table 8-2
For some of the vectors, certain bits will always be 0 (or 1) simply because no
instruction that would set that bit differently can ever end up on that vector. For
example, ISR.sp is always 0 in the Break Instruction vector because ISR.sp is only set
by speculative loads, and speculative loads can never take a Break Instruction fault.
After interruption from the IA-32 instruction set, the following ISR bits will always be
zero: ISR.ni, ISR.na, ISR.sp, ISR.rs, ISR.ir, ISR.ei, and ISR.ed.
ISR.code settings for non-access instructions are described in
and Interruptions" on page
Table 8-3 on page 2:170
Volume 2, Part 1: Interruption Vector Descriptions
describes the interruption mechanism and programming model for the
"IA-32 Interruption Vector Definitions"
defines which interruption resources are written, are left unmodified, or are
"Interruption Control Registers" on page 2:36
provides an overview of ISR settings for all of the interruption vectors.
2:103.
provides an overview of ISR.code field on all Itanium traps.
describes all the Itanium IVA-based interruption
describes all of the IA-32 interrupt
Chapter 11, "Processor Abstraction
"Interruption Definitions" on page
for details on how the processor
2:95.
for the
"Non-access Instructions
2:165
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