Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 337

3. mf ;;
srlz.i ;; // Ensure visibility of ptc.ga to local instruction stream
After step 3, no processor in the coherence domain will initiate new memory
references or prefetches to the old translation. Note, however, that memory
references or prefetches initiated to the old translation prior to step 2 may still be
in progress after step 3. These outstanding memory references and prefetches
may return instructions or data which may be placed in the processor cache
hierarchy; this behavior is implementation-specific.
If the new memory attribute is an uncacheable attribute, and if the old attribute
was cacheable (or if it is not known at this point in the code sequence what the
old attribute was), then software must drain any current prefetches and ensure
that any cached data from the page is removed from caches. To do this, software
must perform steps 4-10. If the new memory attribute is cacheable, then
software may skip steps 4-10, and go straight to step 11.
4. Call PAL_PREFETCH_VISIBILITY
Call PAL_PREFETCH_VISIBILITY with the input argument trans_type equal to zero
to indicate that the transition is for virtual memory attributes. The return
argument from this procedure informs the caller if this procedure call is needed
on remote processors or not. If this procedure call is not needed on remote
processors, then software may skip the IPI in step 5 and go straight to step 6
below.
5. Using the IPI mechanism defined in
page 2:128
above on all processors in the coherence domain, and wait for all
PAL_PREFETCH_VISIBILITY calls to complete on all processors in the coherence
domain before continuing.
After steps 4 and 5, no more new instruction or data prefetches will be made to
page "X" by any processor in the coherence domain. However, processor caches
in the coherence domain may still contain "stale" data or instructions from prior
prefetch or memory references to page "X."
6. Insert a temporary UC translation for page "X."
7. fc [X] // flush all processor caches in the coherence domain
fc [X+32]
fc [X+64]
... // ... for all of page "X" (page size = ps)
fc [X+ps-32] ;;
// Ensure cache flushes are also seen by processors' instruction
fetch
sync.i ;;
After step 7, all flush cache instructions initiated in step 7 are visible to all
processors in the coherence domain, i.e., no processor in the coherence domain
will respond with a cache hit on a memory reference to an address belonging to
page "X."
8. Purge the temporary UC translation from the TLB
Volume 2, Part 1: Addressing and Protection
// Ensure visibility of ptc.ga to local data stream
to reach all processors in the coherence domain, perform step 4
"Inter-processor Interrupt Messages" on
2:89