Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 341

8. If PAL_CACHE_FLUSH is used to flush caches, it must also be called on all
processors in the coherency domain. In any case, PAL_MC_DRAIN must be called
on all processors. Using the IPI mechanism defined in
"Inter-processor Interrupt Messages" on page 2:128
the coherence domain, perform step 6.a, if necessary, and step 7 above in that
order on all processors in the coherence domain, and wait for all PAL_MC_DRAIN
calls to complete on all processors in the coherence domain before continuing.
This further guarantees that any cache lines containing addresses belonging to
page [X] have been evicted from all caches in the coherence domain and forced
onto the platform fabric. Note that this operation does not ensure that the cache
lines have been written back to memory.
9. Perform whatever platform dependent actions are necessary to flush any platform
caches of any copies of the memory being OLDed and to force all cache lines back
to the memory being OLDed. (Note: Refer to platform specific documentation.)
This sequence ensures that speculation and prefetching is disabled for the memory
range, regardless of WB or WBL attribute, that all in-flight prefetches are completed,
and that all caches lines are returned to memory.
4.5 Memory Datum Alignment and Atomicity
All Itanium instruction fetches, aligned load, store and semaphore operations (including
IA-32) are atomic, except for floating-point extended memory references (ldfe, stfe,
and IA-32 10-byte memory references) to non-write-back cacheable memory. In some
processor models, aligned 10-byte Itanium floating-point extended memory references
to non-write-back cacheable memory may raise an Unsupported Data Reference fault.
See "Effects of Memory Attributes on Memory Reference Instructions" on page 2:86
details. Loads are allowed to be satisfied with values obtained from a store buffer (or
any logically equivalent structure) where architectural ordering permits, and values
loaded may appear to be non-atomic. For details, refer to
Ordering" on page
Load pair instructions are performed atomically under the following conditions: a
16-byte aligned load integer/double pair is performed as an atomic 16-byte memory
reference. An 8-byte aligned load single pair is performed as an atomic 8-byte memory
reference.
An aligned ld16 or st16 instruction is performed as an atomic 16-byte memory
reference. For these instructions, the address specified must be 16-byte aligned.
Unaligned ld16 and st16 instructions result in an Unaligned Data Reference fault
regardless of the state of PSR.ac.
Aligned Itanium data memory references never raise an Unaligned Data Reference
fault. Minimally, each Itanium instruction and its corresponding template are fetched
together atomically. Itanium unordered loads can use the store buffer for data values.
See "Sequentiality Attribute and Ordering" on page 2:82
When PSR.ac is 1, any Itanium data memory reference that is not aligned on a
boundary the size of the operand results in an Unaligned Data Reference fault; e.g., 1,
2, 4, 8, 10, and 16-byte datums should be aligned on 1, 2, 4, 8, 16, and 16-byte
Volume 2, Part 1: Addressing and Protection
2:82.
Section 5.8.4.1,
to reach all processors in
"Sequentiality Attribute and
for details.
for
2:93