Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 294

Figure 4-1.
By assigning sequential region identifiers, regions can be coalesced to produce larger
62-, 63- or 64-bit spaces. For example, an operating system could implement a 62-bit
region for process private data, 62-bit region for I/O, and a 63-bit region for globally
shared data. Default page sizes and translation policies can be assigned to each virtual
region.
Figure 4-2
Each virtual address is composed of three fields: the Virtual Region Number, the Virtual
Page Number, and the page offset. The upper 3-bits select the Virtual Region Number
(VRN). The least-significant bits form the page offset. The Virtual Page Number (VPN)
consists of the remaining bits. The VRN bits are not included in the VPN. The page
offset bits are passed through the translation process unmodified. Exact bit positions
for the page offset and VPN bits vary depending on the page size used in the virtual
mapping.
On a memory reference (any reference other than an insert or purge), the VRN bits
select a Region Identifier (RID) from 1 of the 8 region registers, the TLB is then
searched for a translation entry with a matching VPN and RID value. The VRN may
optionally be used when searching for a matching translation on memory references
(references other than inserts and purges
Inserts and Purges"). If a matching translation entry is found, the entry's physical page
number (PPN) is concatenated with the page offset bits to form the physical address.
Matching translations are qualified by page-granular privilege level access right checks
and optional protection domain checks by verifying the translation's key is contained
within a set of protection key registers and read, write, execute permissions are
granted.
If the required translation is not resident in the TLB, the processor may optionally
search the VHPT structure in memory for the required translation and install the entry
into the TLB. If the required entry cannot be found in the TLB and/or VHPT, the
processor raises a TLB Miss fault to request that the operating system supply the
translation. After the operating system installs the translation in the TLB and/or VHPT,
the faulting instruction can be restarted and execution resumed.
2:46
Virtual Address Spaces
63
8 Virtual
Regions
0
61
2 Bytes
4K to 256M
Per Region Pages
shows the process of mapping a virtual address into a physical address.
Virtual Address
3
1
24
2
Address Spaces
see Section 4.1.1.4, "Purge Behavior of TLB
–
Volume 2, Part 1: Addressing and Protection
0
Virtual